LXR uboot/board/freescale/common/qixis.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2011 Freescale Semiconductor
   4 * Copyright 2020 NXP
   5 * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
   6 *
   7 * This file provides support for the QIXIS of some Freescale reference boards.
   8 */
   9
  10#ifndef __QIXIS_H_
  11#define __QIXIS_H_
  12
  13struct qixis {
  14        u8 id;      /* ID value uniquely identifying each QDS board type */
  15        u8 arch;    /* Board version information */
  16        u8 scver;   /* QIXIS Version Register */
  17        u8 model;   /* Information of software programming model version */
  18        u8 tagdata;
  19        u8 ctl_sys;
  20        u8 aux;         /* Auxiliary Register,0x06 */
  21        u8 clk_spd;
  22        u8 stat_dut;
  23        u8 stat_sys;
  24        u8 stat_alrm;
  25        u8 present;
  26        u8 present2;    /* Presence Status Register 2,0x0c */
  27        u8 rcw_ctl;
  28        u8 ctl_led;
  29        u8 i2cblk;
  30        u8 rcfg_ctl;    /* Reconfig Control Register,0x10 */
  31        u8 rcfg_st;
  32        u8 dcm_ad;
  33        u8 dcm_da;
  34        u8 dcmd;
  35        u8 dmsg;
  36        u8 gdc;
  37        u8 gdd;         /* DCM Debug Data Register,0x17 */
  38        u8 dmack;
  39        u8 res1;
  40        u8 sdhc1;
  41        u8 sdhc2;
  42        u8 stat_pres3;
  43        u8 los_stat;
  44        u8 usb_ctl;
  45        u8 watch;       /* Watchdog Register,0x1F */
  46        u8 pwr_ctl[2];  /* Power Control Register,0x20 */
  47        u8 res2[2];
  48        u8 pwr_stat[4]; /* Power Status Register,0x24 */
  49        u8 res3[8];
  50        u8 clk_spd2[2];  /* SYSCLK clock Speed Register,0x30 */
  51        u8 res4[2];
  52        u8 sclk[3];  /* Clock Configuration Registers,0x34 */
  53        u8 res5;
  54        u8 dclk[3];
  55        u8 res6;
  56        u8 clk_dspd[3];
  57        u8 res7;
  58        u8 rst_ctl;     /* Reset Control Register,0x40 */
  59        u8 rst_stat;    /* Reset Status Register */
  60        u8 rst_rsn;     /* Reset Reason Register */
  61        u8 rst_frc[2];  /* Reset Force Registers,0x43 */
  62        u8 res8[11];
  63        u8 brdcfg[16];  /* Board Configuration Register,0x50 */
  64        u8 dutcfg[16];
  65        u8 rcw_ad[2];   /* RCW SRAM Address Registers,0x70 */
  66        u8 rcw_data;
  67        u8 res9[5];
  68        u8 post_ctl;
  69        u8 post_stat;
  70        u8 post_dat[2];
  71        u8 pi_d[4];
  72        u8 gpio_io[4];
  73        u8 gpio_dir[4];
  74        u8 res10[20];
  75        u8 rjtag_ctl;
  76        u8 rjtag_dat;
  77        u8 res11[2];
  78        u8 trig_src[4];
  79        u8 trig_dst[4];
  80        u8 trig_stat;
  81        u8 res12[3];
  82        u8 trig_ctr[4];
  83        u8 res13[16];
  84        u8 clk_freq[6]; /* Clock Measurement Registers */
  85        u8 res_c6[8];
  86        u8 clk_base[2]; /* Clock Frequency Base Reg */
  87        u8 res_d0[8];
  88        u8 cms[2];      /* Core Management Space Address Register, 0xD8 */
  89        u8 res_c0[6];
  90        u8 aux2[4];     /* Auxiliary Registers,0xE0 */
  91        u8 res14[10];
  92        u8 aux_ad;
  93        u8 aux_da;
  94        u8 res15[16];
  95};
  96
  97u8 qixis_read(unsigned int reg);
  98void qixis_write(unsigned int reg, u8 value);
  99u16 qixis_read_minor(void);
 100char *qixis_read_time(char *result);
 101char *qixis_read_tag(char *buf);
 102const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
 103#ifdef CONFIG_SYS_I2C_FPGA_ADDR
 104u8 qixis_read_i2c(unsigned int reg);
 105void qixis_write_i2c(unsigned int reg, u8 value);
 106#endif
 107
 108#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
 109#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
 110#define QIXIS_WRITE(reg, value) \
 111        qixis_write_i2c(offsetof(struct qixis, reg), value)
 112#else
 113#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
 114#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
 115#endif
 116
 117#ifdef CONFIG_SYS_I2C_FPGA_ADDR
 118#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
 119#define QIXIS_WRITE_I2C(reg, value) \
 120                        qixis_write_i2c(offsetof(struct qixis, reg), value)
 121#endif
 122
 123/* Use for SDHC adapter card type identification and operation */
 124#define QIXIS_SDID_MASK                         0x07
 125
 126#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45         0x1     /* eMMC Card Rev4.5 */
 127#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY   0x2     /* SD/MMC Legacy Card */
 128#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44         0x3     /* eMMC Card Rev4.4 */
 129#define QIXIS_ESDHC_ADAPTER_TYPE_RSV            0x4     /* Reserved */
 130#define QIXIS_ESDHC_ADAPTER_TYPE_MMC            0x5     /* MMC Card */
 131#define QIXIS_ESDHC_ADAPTER_TYPE_SD             0x6     /* SD Card Rev2.0 3.0 */
 132#define QIXIS_ESDHC_NO_ADAPTER                  0x7     /* No Card is Present*/
 133
 134#define QIXIS_SDHC1_S1V3        0x80    /* SDHC1: SDHC1 3.3V power control */
 135#define QIXIS_SDHC1_VS          0x30    /* BRDCFG11: route to SDHC1_VS */
 136
 137#define QIXIS_SDCLKIN           0x08
 138#define QIXIS_SDCLKOUT          0x02
 139#define QIXIS_DAT5_6_7          0X02
 140#define QIXIS_DAT4              0X01
 141
 142#define QIXIS_EVDD_BY_SDHC_VS   0x0c
 143
 144#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
 145defined(CONFIG_TARGET_LX2160ARDB)
 146#define QIXIS_XMAP_MASK                 0x07
 147#define QIXIS_RST_CTL_RESET_EN          0x30
 148#define QIXIS_LBMAP_DFLTBANK            0x00
 149#define QIXIS_LBMAP_ALTBANK             0x20
 150#define QIXIS_LBMAP_QSPI                0x00
 151#define QIXIS_RCW_SRC_QSPI              0xff
 152#define QIXIS_RST_CTL_RESET             0x31
 153#define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 154#define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 155#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 156#define QIXIS_LBMAP_MASK                0x0f
 157#define QIXIS_LBMAP_SD
 158#define QIXIS_LBMAP_EMMC
 159#define QIXIS_RCW_SRC_SD                0x08
 160#define QIXIS_RCW_SRC_EMMC         0x09
 161#define NON_EXTENDED_DUTCFG
 162#endif
 163
 164#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 165#define QIXIS_SDID_MASK                 0x07
 166#define QIXIS_ESDHC_NO_ADAPTER          0x7
 167#endif
 168
 169#endif
 170