LXR uboot/board/freescale/ls1012ardb/ls1012ardb.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2016 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <command.h>
   8#include <fdt_support.h>
   9#include <hang.h>
  10#include <i2c.h>
  11#include <asm/cache.h>
  12#include <init.h>
  13#include <asm/io.h>
  14#include <asm/arch/clock.h>
  15#include <asm/arch/fsl_serdes.h>
  16#ifdef CONFIG_FSL_LS_PPA
  17#include <asm/arch/ppa.h>
  18#endif
  19#include <asm/arch/mmu.h>
  20#include <asm/arch/soc.h>
  21#include <hwconfig.h>
  22#include <ahci.h>
  23#include <mmc.h>
  24#include <scsi.h>
  25#include <fsl_esdhc.h>
  26#include <env_internal.h>
  27#include <fsl_mmdc.h>
  28#include <netdev.h>
  29#include <fsl_sec.h>
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33#define BOOT_FROM_UPPER_BANK    0x2
  34#define BOOT_FROM_LOWER_BANK    0x1
  35
  36int checkboard(void)
  37{
  38#ifdef CONFIG_TARGET_LS1012ARDB
  39        u8 in1;
  40        int ret, bus_num = 0;
  41
  42        puts("Board: LS1012ARDB ");
  43
  44        /* Initialize i2c early for Serial flash bank information */
  45#if defined(CONFIG_DM_I2C)
  46        struct udevice *dev;
  47
  48        ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
  49                                      1, &dev);
  50        if (ret) {
  51                printf("%s: Cannot find udev for a bus %d\n", __func__,
  52                       bus_num);
  53                return -ENXIO;
  54        }
  55        ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
  56#else /* Non DM I2C support - will be removed */
  57        i2c_set_bus_num(bus_num);
  58        ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
  59#endif
  60        if (ret < 0) {
  61                printf("Error reading i2c boot information!\n");
  62                return 0; /* Don't want to hang() on this error */
  63        }
  64
  65        puts("Version");
  66        switch (in1 & SW_REV_MASK) {
  67        case SW_REV_A:
  68                puts(": RevA");
  69                break;
  70        case SW_REV_B:
  71                puts(": RevB");
  72                break;
  73        case SW_REV_C:
  74                puts(": RevC");
  75                break;
  76        case SW_REV_C1:
  77                puts(": RevC1");
  78                break;
  79        case SW_REV_C2:
  80                puts(": RevC2");
  81                break;
  82        case SW_REV_D:
  83                puts(": RevD");
  84                break;
  85        case SW_REV_E:
  86                puts(": RevE");
  87                break;
  88        default:
  89                puts(": unknown");
  90                break;
  91        }
  92
  93        printf(", boot from QSPI");
  94        if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
  95                puts(": emu\n");
  96        else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
  97                puts(": bank1\n");
  98        else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
  99                puts(": bank2\n");
 100        else
 101                puts("unknown\n");
 102#else
 103
 104        puts("Board: LS1012A2G5RDB ");
 105#endif
 106        return 0;
 107}
 108
 109#ifdef CONFIG_TFABOOT
 110int dram_init(void)
 111{
 112        gd->ram_size = tfa_get_dram_size();
 113        if (!gd->ram_size)
 114                gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 115
 116        return 0;
 117}
 118#else
 119int dram_init(void)
 120{
 121#ifndef CONFIG_TFABOOT
 122        static const struct fsl_mmdc_info mparam = {
 123                0x05180000,     /* mdctl */
 124                0x00030035,     /* mdpdc */
 125                0x12554000,     /* mdotc */
 126                0xbabf7954,     /* mdcfg0 */
 127                0xdb328f64,     /* mdcfg1 */
 128                0x01ff00db,     /* mdcfg2 */
 129                0x00001680,     /* mdmisc */
 130                0x0f3c8000,     /* mdref */
 131                0x00002000,     /* mdrwd */
 132                0x00bf1023,     /* mdor */
 133                0x0000003f,     /* mdasp */
 134                0x0000022a,     /* mpodtctrl */
 135                0xa1390003,     /* mpzqhwctrl */
 136        };
 137
 138        mmdc_init(&mparam);
 139#endif
 140
 141        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 142#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 143        /* This will break-before-make MMU for DDR */
 144        update_early_mmu_table();
 145#endif
 146
 147        return 0;
 148}
 149#endif
 150
 151
 152int board_early_init_f(void)
 153{
 154        fsl_lsch2_early_init_f();
 155
 156        return 0;
 157}
 158
 159int board_init(void)
 160{
 161        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 162                                        CONFIG_SYS_CCI400_OFFSET);
 163        /*
 164         * Set CCI-400 control override register to enable barrier
 165         * transaction
 166         */
 167        if (current_el() == 3)
 168                out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 169
 170#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 171        erratum_a010315();
 172#endif
 173
 174#ifdef CONFIG_ENV_IS_NOWHERE
 175        gd->env_addr = (ulong)&default_environment[0];
 176#endif
 177
 178#ifdef CONFIG_FSL_CAAM
 179        sec_init();
 180#endif
 181
 182#ifdef CONFIG_FSL_LS_PPA
 183        ppa_init();
 184#endif
 185        return 0;
 186}
 187
 188#ifdef CONFIG_TARGET_LS1012ARDB
 189int esdhc_status_fixup(void *blob, const char *compat)
 190{
 191        char esdhc1_path[] = "/soc/esdhc@1580000";
 192        bool sdhc2_en = false;
 193        u8 mux_sdhc2;
 194        u8 io = 0;
 195        int ret, bus_num = 0;
 196
 197#if defined(CONFIG_DM_I2C)
 198        struct udevice *dev;
 199
 200        ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
 201                                      1, &dev);
 202        if (ret) {
 203                printf("%s: Cannot find udev for a bus %d\n", __func__,
 204                       bus_num);
 205                return -ENXIO;
 206        }
 207        ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
 208#else
 209        i2c_set_bus_num(bus_num);
 210        /* IO1[7:3] is the field of board revision info. */
 211        ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
 212#endif
 213        if (ret < 0) {
 214                printf("Error reading i2c boot information!\n");
 215                return 0;
 216        }
 217
 218        /* hwconfig method is used for RevD and later versions. */
 219        if ((io & SW_REV_MASK) <= SW_REV_D) {
 220#ifdef CONFIG_HWCONFIG
 221                if (hwconfig("esdhc1"))
 222                        sdhc2_en = true;
 223#endif
 224        } else {
 225                /*
 226                 * The I2C IO-expander for mux select is used to control
 227                 * the muxing of various onboard interfaces.
 228                 *
 229                 * IO0[3:2] indicates SDHC2 interface demultiplexer
 230                 * select lines.
 231                 *      00 - SDIO wifi
 232                 *      01 - GPIO (to Arduino)
 233                 *      10 - eMMC Memory
 234                 *      11 - SPI
 235                 */
 236#if defined(CONFIG_DM_I2C)
 237                ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
 238#else
 239                ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
 240#endif
 241                if (ret < 0) {
 242                        printf("Error reading i2c boot information!\n");
 243                        return 0;
 244                }
 245
 246                mux_sdhc2 = (io & 0x0c) >> 2;
 247                /* Enable SDHC2 only when use SDIO wifi and eMMC */
 248                if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
 249                        sdhc2_en = true;
 250        }
 251        if (sdhc2_en)
 252                do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 253                                 sizeof("okay"), 1);
 254        else
 255                do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 256                                 sizeof("disabled"), 1);
 257        return 0;
 258}
 259#endif
 260
 261int ft_board_setup(void *blob, struct bd_info *bd)
 262{
 263        arch_fixup_fdt(blob);
 264
 265        ft_cpu_setup(blob, bd);
 266
 267        return 0;
 268}
 269
 270static int switch_to_bank1(void)
 271{
 272        u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
 273        int ret, bus_num = 0;
 274
 275#if defined(CONFIG_DM_I2C)
 276        struct udevice *dev;
 277
 278        ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
 279                                      1, &dev);
 280        if (ret) {
 281                printf("%s: Cannot find udev for a bus %d\n", __func__,
 282                       bus_num);
 283                return -ENXIO;
 284        }
 285        /*
 286         * --------------------------------------------------------------------
 287         * |bus |I2C address|       Device     |          Notes               |
 288         * --------------------------------------------------------------------
 289         * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General   |
 290         * |    |0x26       | RESET, and INT/  | Purpose parallel Input/Output|
 291         * |    |           | KW41GPIO) - NXP  | (GPIO) expansion for the     |
 292         * |    |           | PCAL9555AHF      | I2C bus                      |
 293         * ----- --------------------------------------------------------------
 294         * - mount three IO expander(PCAL9555AHF) on I2C1
 295         *
 296         * PCAL9555A device address
 297         *           slave address
 298         *  --------------------------------------
 299         *  | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
 300         *  --------------------------------------
 301         *  |     fixed     | hardware selectable|
 302         *
 303         * Output port 1(Pinter register bits = 0x03)
 304         *
 305         * P1_[7~0] = 0xf4
 306         * P1_0 <---> CFG_MUX_QSPI_S0
 307         * P1_1 <---> CFG_MUX_QSPI_S1
 308         * CFG_MUX_QSPI_S[1:0] = 0b00
 309         *
 310         * QSPI chip-select demultiplexer select
 311         * ---------------------------------------------------------------------
 312         * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0|              Values
 313         * ---------------------------------------------------------------------
 314         *    0           | 0            |CS routed to SPI memory bank1(default)
 315         * ---------------------------------------------------------------------
 316         *    0           | 1             |CS routed to SPI memory bank2
 317         * ---------------------------------------------------------------------
 318         *
 319         */
 320        ret = dm_i2c_write(dev, offset_addr, &data, 1);
 321#else /* Non DM I2C support - will be removed */
 322        i2c_set_bus_num(bus_num);
 323        ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
 324#endif
 325
 326        if (ret) {
 327                printf("i2c write error to chip : %u, addr : %u, data : %u\n",
 328                       chip_addr, offset_addr, data);
 329        }
 330
 331        return ret;
 332}
 333
 334static int switch_to_bank2(void)
 335{
 336        u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
 337        u8 chip_addr = 0x24;
 338        int ret, i, bus_num = 0;
 339
 340#if defined(CONFIG_DM_I2C)
 341        struct udevice *dev;
 342
 343        ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
 344                                      1, &dev);
 345        if (ret) {
 346                printf("%s: Cannot find udev for a bus %d\n", __func__,
 347                       bus_num);
 348                return -ENXIO;
 349        }
 350#else /* Non DM I2C support - will be removed */
 351        i2c_set_bus_num(bus_num);
 352#endif
 353
 354        /*
 355         * 1th step: config port 1
 356         *      - the port 1 pin is enabled as an output
 357         * 2th step: output port 1
 358         *      - P1_[7:0] output 0xf5,
 359         *        then CFG_MUX_QSPI_S[1:0] equal to 0b01,
 360         *        CS routed to SPI memory bank2
 361         */
 362        for (i = 0; i < sizeof(data); i++) {
 363#if defined(CONFIG_DM_I2C)
 364                ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
 365#else /* Non DM I2C support - will be removed */
 366                ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
 367#endif
 368                if (ret) {
 369                        printf("i2c write error to chip : %u, addr : %u, data : %u\n",
 370                               chip_addr, offset_addr[i], data[i]);
 371                        goto err;
 372                }
 373        }
 374
 375err:
 376        return ret;
 377}
 378
 379static int convert_flash_bank(int bank)
 380{
 381        int ret = 0;
 382
 383        switch (bank) {
 384        case BOOT_FROM_UPPER_BANK:
 385                ret = switch_to_bank2();
 386                break;
 387        case BOOT_FROM_LOWER_BANK:
 388                ret = switch_to_bank1();
 389                break;
 390        default:
 391                ret = CMD_RET_USAGE;
 392                break;
 393        };
 394
 395        return ret;
 396}
 397
 398static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 399                          char *const argv[])
 400{
 401        if (argc != 2)
 402                return CMD_RET_USAGE;
 403        if (strcmp(argv[1], "1") == 0)
 404                convert_flash_bank(BOOT_FROM_LOWER_BANK);
 405        else if (strcmp(argv[1], "2") == 0)
 406                convert_flash_bank(BOOT_FROM_UPPER_BANK);
 407        else
 408                return CMD_RET_USAGE;
 409
 410        return 0;
 411}
 412
 413U_BOOT_CMD(
 414        boot_bank, 2, 0, flash_bank_cmd,
 415        "Flash bank Selection Control",
 416        "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
 417);
 418