LXR uboot/board/freescale/ls2080aqds/ddr.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2015 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <fsl_ddr_sdram.h>
   8#include <fsl_ddr_dimm_params.h>
   9#include <log.h>
  10#include <asm/arch/soc.h>
  11#include <asm/arch/clock.h>
  12#include "ddr.h"
  13
  14DECLARE_GLOBAL_DATA_PTR;
  15
  16void fsl_ddr_board_options(memctl_options_t *popts,
  17                                dimm_params_t *pdimm,
  18                                unsigned int ctrl_num)
  19{
  20#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  21        u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
  22#endif
  23        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  24        ulong ddr_freq;
  25        int slot;
  26
  27        if (ctrl_num > 2) {
  28                printf("Not supported controller number %d\n", ctrl_num);
  29                return;
  30        }
  31
  32        for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
  33                if (pdimm[slot].n_ranks)
  34                        break;
  35        }
  36
  37        if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
  38                return;
  39
  40        /*
  41         * we use identical timing for all slots. If needed, change the code
  42         * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  43         */
  44        if (popts->registered_dimm_en)
  45                pbsp = rdimms[ctrl_num];
  46        else
  47                pbsp = udimms[ctrl_num];
  48
  49
  50        /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  51         * freqency and n_banks specified in board_specific_parameters table.
  52         */
  53        ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
  54        while (pbsp->datarate_mhz_high) {
  55                if (pbsp->n_ranks == pdimm[slot].n_ranks &&
  56                    (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
  57                        if (ddr_freq <= pbsp->datarate_mhz_high) {
  58                                popts->clk_adjust = pbsp->clk_adjust;
  59                                popts->wrlvl_start = pbsp->wrlvl_start;
  60                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  61                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  62                                goto found;
  63                        }
  64                        pbsp_highest = pbsp;
  65                }
  66                pbsp++;
  67        }
  68
  69        if (pbsp_highest) {
  70                printf("Error: board specific timing not found for data rate %lu MT/s\n"
  71                        "Trying to use the highest speed (%u) parameters\n",
  72                        ddr_freq, pbsp_highest->datarate_mhz_high);
  73                popts->clk_adjust = pbsp_highest->clk_adjust;
  74                popts->wrlvl_start = pbsp_highest->wrlvl_start;
  75                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  76                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  77        } else {
  78                panic("DIMM is not supported by this board");
  79        }
  80found:
  81        debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  82                "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  83                pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  84                pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  85                pbsp->wrlvl_ctl_3);
  86#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  87        if (ctrl_num == CONFIG_DP_DDR_CTRL) {
  88                /* force DDR bus width to 32 bits */
  89                popts->data_bus_width = 1;
  90                popts->otf_burst_chop_en = 0;
  91                popts->burst_length = DDR_BL8;
  92                popts->bstopre = 0;     /* enable auto precharge */
  93                /*
  94                 * Layout optimization results byte mapping
  95                 * Byte 0 -> Byte ECC
  96                 * Byte 1 -> Byte 3
  97                 * Byte 2 -> Byte 2
  98                 * Byte 3 -> Byte 1
  99                 * Byte ECC -> Byte 0
 100                 */
 101                dq_mapping_0 = pdimm[slot].dq_mapping[0];
 102                dq_mapping_2 = pdimm[slot].dq_mapping[2];
 103                dq_mapping_3 = pdimm[slot].dq_mapping[3];
 104                pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
 105                pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
 106                pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
 107                pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
 108                pdimm[slot].dq_mapping[6] = dq_mapping_2;
 109                pdimm[slot].dq_mapping[7] = dq_mapping_3;
 110                pdimm[slot].dq_mapping[8] = dq_mapping_0;
 111                pdimm[slot].dq_mapping[9] = 0;
 112                pdimm[slot].dq_mapping[10] = 0;
 113                pdimm[slot].dq_mapping[11] = 0;
 114                pdimm[slot].dq_mapping[12] = 0;
 115                pdimm[slot].dq_mapping[13] = 0;
 116                pdimm[slot].dq_mapping[14] = 0;
 117                pdimm[slot].dq_mapping[15] = 0;
 118                pdimm[slot].dq_mapping[16] = 0;
 119                pdimm[slot].dq_mapping[17] = 0;
 120        }
 121#endif
 122        /* To work at higher than 1333MT/s */
 123        popts->half_strength_driver_enable = 0;
 124        /*
 125         * Write leveling override
 126         */
 127        popts->wrlvl_override = 1;
 128        popts->wrlvl_sample = 0x0;      /* 32 clocks */
 129
 130        /*
 131         * Rtt and Rtt_WR override
 132         */
 133        popts->rtt_override = 0;
 134
 135        /* Enable ZQ calibration */
 136        popts->zq_en = 1;
 137
 138        if (ddr_freq < 2350) {
 139                if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
 140                        /* four chip-selects */
 141                        popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
 142                                          DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 143                        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
 144                        popts->twot_en = 1; /* enable 2T timing */
 145                } else {
 146                        popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
 147                                          DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
 148                        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
 149                                          DDR_CDR2_VREF_RANGE_2;
 150                }
 151        } else {
 152                popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
 153                                  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
 154                popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
 155                                  DDR_CDR2_VREF_RANGE_2;
 156        }
 157}
 158
 159#ifdef CONFIG_TFABOOT
 160int fsl_initdram(void)
 161{
 162        gd->ram_size = tfa_get_dram_size();
 163
 164        if (!gd->ram_size)
 165                gd->ram_size = fsl_ddr_sdram_size();
 166
 167        return 0;
 168}
 169#else
 170int fsl_initdram(void)
 171{
 172#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 173        gd->ram_size = fsl_ddr_sdram_size();
 174#else
 175        puts("Initializing DDR....using SPD\n");
 176
 177        gd->ram_size = fsl_ddr_sdram();
 178#endif
 179
 180        return 0;
 181}
 182#endif /* CONFIG_TFABOOT */
 183