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6#include <common.h>
7#include <init.h>
8#include <net.h>
9#include <asm/io.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/arch/crm_regs.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/iomux-mx53.h>
15#include <linux/errno.h>
16#include <netdev.h>
17#include <mmc.h>
18#include <fsl_esdhc_imx.h>
19#include <asm/gpio.h>
20
21#define ETHERNET_INT IMX_GPIO_NR(2, 31)
22
23DECLARE_GLOBAL_DATA_PTR;
24
25int dram_init(void)
26{
27 u32 size1, size2;
28
29 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
30 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
31
32 gd->ram_size = size1 + size2;
33
34 return 0;
35}
36int dram_init_banksize(void)
37{
38 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
39 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
40
41 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
42 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
43
44 return 0;
45}
46
47#ifdef CONFIG_NAND_MXC
48static void setup_iomux_nand(void)
49{
50 static const iomux_v3_cfg_t nand_pads[] = {
51 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
52 PAD_CTL_DSE_HIGH),
53 NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
54 PAD_CTL_DSE_HIGH),
55 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
56 PAD_CTL_PUS_100K_UP),
57 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
58 PAD_CTL_DSE_HIGH),
59 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
60 PAD_CTL_DSE_HIGH),
61 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
62 PAD_CTL_PUS_100K_UP),
63 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
64 PAD_CTL_DSE_HIGH),
65 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
66 PAD_CTL_DSE_HIGH),
67 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
68 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
69 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
70 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
71 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
72 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
73 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
74 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
75 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
76 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
77 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
78 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
79 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
80 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
81 NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
82 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
83 };
84
85 u32 i, reg;
86
87 reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
88 reg &= ~M4IF_GENP_WEIM_MM_MASK;
89 __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
90 for (i = 0x4; i < 0x94; i += 0x18) {
91 reg = __raw_readl(WEIM_BASE_ADDR + i);
92 reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
93 __raw_writel(reg, WEIM_BASE_ADDR + i);
94 }
95
96 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
97}
98#else
99static void setup_iomux_nand(void)
100{
101}
102#endif
103
104#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
105 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
106
107static void setup_iomux_uart(void)
108{
109 static const iomux_v3_cfg_t uart_pads[] = {
110 NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
111 NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
112 };
113
114 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
115}
116
117#ifdef CONFIG_FSL_ESDHC_IMX
118struct fsl_esdhc_cfg esdhc_cfg[2] = {
119 {MMC_SDHC1_BASE_ADDR},
120 {MMC_SDHC2_BASE_ADDR},
121};
122
123int board_mmc_getcd(struct mmc *mmc)
124{
125 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
126 int ret;
127
128 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
129 gpio_direction_input(IMX_GPIO_NR(1, 1));
130 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
131 gpio_direction_input(IMX_GPIO_NR(1, 4));
132
133 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
134 ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
135 else
136 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
137
138 return ret;
139}
140
141#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
142 PAD_CTL_PUS_100K_UP)
143#define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
144#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
145 PAD_CTL_DSE_HIGH)
146
147int board_mmc_init(struct bd_info *bis)
148{
149 static const iomux_v3_cfg_t sd1_pads[] = {
150 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
151 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
152 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
153 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
154 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
155 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
156 };
157
158 static const iomux_v3_cfg_t sd2_pads[] = {
159 NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
160 NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
161 NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
162 NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
163 NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
164 NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
165 NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
166 NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
167 NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
168 NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
169 };
170
171 u32 index;
172 int ret;
173
174 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
175 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
176
177 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
178 switch (index) {
179 case 0:
180 imx_iomux_v3_setup_multiple_pads(sd1_pads,
181 ARRAY_SIZE(sd1_pads));
182 break;
183 case 1:
184 imx_iomux_v3_setup_multiple_pads(sd2_pads,
185 ARRAY_SIZE(sd2_pads));
186 break;
187 default:
188 printf("Warning: you configured more ESDHC controller"
189 "(%d) as supported by the board(2)\n",
190 CONFIG_SYS_FSL_ESDHC_NUM);
191 return -EINVAL;
192 }
193 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
194 if (ret)
195 return ret;
196 }
197
198 return 0;
199}
200#endif
201
202static void weim_smc911x_iomux(void)
203{
204 static const iomux_v3_cfg_t weim_smc911x_pads[] = {
205
206 NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
207 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
208 NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
209 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
210 NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
211 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
212 NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
213 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
214 NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
215 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
216 NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
217 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
218 NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
219 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
220 NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
221 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
222 NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
223 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
224 NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
225 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
226 NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
227 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
228 NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
229 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
230 NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
231 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
232 NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
233 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
234 NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
235 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
236 NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
237 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
238
239
240 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
241 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
242 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
243 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
244 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
245 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
246 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
247 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
248 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
249 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
250 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
251 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
252 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
253 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
254
255
256 MX53_PAD_EIM_OE__EMI_WEIM_OE,
257 MX53_PAD_EIM_RW__EMI_WEIM_RW,
258 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
259 };
260
261
262 imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
263 gpio_direction_input(ETHERNET_INT);
264
265
266 imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
267 ARRAY_SIZE(weim_smc911x_pads));
268}
269
270static void weim_cs1_settings(void)
271{
272 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
273
274 writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
275 writel(0x0, &weim_regs->cs1gcr2);
276 writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
277 writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
278 writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
279 writel(0x0, &weim_regs->cs1wcr2);
280 writel(0x0, &weim_regs->wcr);
281
282 set_chipselect_size(CS0_64M_CS1_64M);
283}
284
285int board_early_init_f(void)
286{
287 setup_iomux_nand();
288 setup_iomux_uart();
289 return 0;
290}
291
292int board_init(void)
293{
294
295 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
296
297 return 0;
298}
299
300int board_eth_init(struct bd_info *bis)
301{
302 int rc = -ENODEV;
303
304 weim_smc911x_iomux();
305 weim_cs1_settings();
306
307#ifdef CONFIG_SMC911X
308 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
309#endif
310 return rc;
311}
312
313int checkboard(void)
314{
315 puts("Board: MX53ARD\n");
316
317 return 0;
318}
319
