LXR uboot/board/freescale/mx6memcal/spl.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2016 Nelson Integration, LLC
   4 * Author: Eric Nelson <eric@nelint.com>
   5 */
   6
   7#include <common.h>
   8#include <cpu_func.h>
   9#include <init.h>
  10#include <asm/io.h>
  11#include <asm/arch/iomux.h>
  12#include <asm/arch/clock.h>
  13#include <asm/arch/crm_regs.h>
  14#include <asm/arch/mx6-ddr.h>
  15#include <asm/arch/mx6-pins.h>
  16#include <asm/arch/sys_proto.h>
  17#include <spl.h>
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  22        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  23        PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  24
  25static iomux_v3_cfg_t const uart_pads[] = {
  26#ifdef CONFIG_UART2_EIM_D26_27
  27        IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  28        IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  29#elif defined(CONFIG_UART1_CSI0_DAT10_11)
  30        IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  31        IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  32#elif defined(CONFIG_UART1_SD3_DAT6_7)
  33        IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  34        IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  35#elif defined(CONFIG_UART1_UART1)
  36        MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  37        MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  38#else
  39#error select UART console pads
  40#endif
  41};
  42
  43#ifdef CONFIG_DDR3
  44#define GRP_DDRTYPE     0x000C0000
  45#else
  46#define GRP_DDRTYPE     0x00080000
  47#endif
  48
  49/* all existing designs have this disabled */
  50#define DDR_PKE         0
  51
  52/* use Kconfig for ODT and DRIVE_STRENGTH */
  53#define DDR_ODT \
  54        (CONFIG_DDR_ODT << 8)
  55#define DRAM_DRIVE_STRENGTH \
  56        (CONFIG_DRAM_DRIVE_STRENGTH << 3)
  57
  58/* configure MX6Q/DUAL mmdc DDR io registers */
  59static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = {
  60        /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  61        .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  62        .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  63        .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
  64        .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
  65        .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
  66        /* SDCKE[0:1]: 100k pull-up */
  67        .dram_sdcke0 = 0x00003000,
  68        .dram_sdcke1 = 0x00003000,
  69        /* SDBA2: pull-up disabled */
  70        .dram_sdba2 = 0x00000000,
  71        /* SDODT[0:1]: 100k pull-up, 40 ohm */
  72        .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
  73        .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
  74        /* SDQS[0:7]: Differential input, 40 ohm */
  75        .dram_sdqs0 = DRAM_DRIVE_STRENGTH,
  76        .dram_sdqs1 = DRAM_DRIVE_STRENGTH,
  77        .dram_sdqs2 = DRAM_DRIVE_STRENGTH,
  78        .dram_sdqs3 = DRAM_DRIVE_STRENGTH,
  79        .dram_sdqs4 = DRAM_DRIVE_STRENGTH,
  80        .dram_sdqs5 = DRAM_DRIVE_STRENGTH,
  81        .dram_sdqs6 = DRAM_DRIVE_STRENGTH,
  82        .dram_sdqs7 = DRAM_DRIVE_STRENGTH,
  83
  84        /* DQM[0:7]: Differential input, 40 ohm */
  85        .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  86        .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  87        .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  88        .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  89        .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  90        .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  91        .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  92        .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  93};
  94
  95/* configure MX6Q/DUAL mmdc GRP io registers */
  96static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = {
  97        /* DDR3 */
  98        .grp_ddr_type = GRP_DDRTYPE,
  99        .grp_ddrmode_ctl = DDR_ODT,
 100        /* disable DDR pullups */
 101        .grp_ddrpke = DDR_PKE,
 102        /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 103        .grp_addds = DRAM_DRIVE_STRENGTH,
 104        /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 105        .grp_ctlds = DRAM_DRIVE_STRENGTH,
 106        /* DATA[00:63]: Differential input, 40 ohm */
 107        .grp_ddrmode = DDR_ODT,
 108        .grp_b0ds = DRAM_DRIVE_STRENGTH,
 109        .grp_b1ds = DRAM_DRIVE_STRENGTH,
 110        .grp_b2ds = DRAM_DRIVE_STRENGTH,
 111        .grp_b3ds = DRAM_DRIVE_STRENGTH,
 112        .grp_b4ds = DRAM_DRIVE_STRENGTH,
 113        .grp_b5ds = DRAM_DRIVE_STRENGTH,
 114        .grp_b6ds = DRAM_DRIVE_STRENGTH,
 115        .grp_b7ds = DRAM_DRIVE_STRENGTH,
 116};
 117
 118static struct mx6sdl_iomux_ddr_regs const mx6sdl_ddr_ioregs = {
 119        /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 120        .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 121        .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 122        .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
 123        .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
 124        .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
 125        /* SDCKE[0:1]: 100k pull-up */
 126        .dram_sdcke0 = 0x00003000,
 127        .dram_sdcke1 = 0x00003000,
 128        /* SDBA2: pull-up disabled */
 129        .dram_sdba2 = 0x00000000,
 130        /* SDODT[0:1]: 100k pull-up, 40 ohm */
 131        .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
 132        .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
 133        /* SDQS[0:7]: Differential input, 40 ohm */
 134        .dram_sdqs0 = DRAM_DRIVE_STRENGTH,
 135        .dram_sdqs1 = DRAM_DRIVE_STRENGTH,
 136        .dram_sdqs2 = DRAM_DRIVE_STRENGTH,
 137        .dram_sdqs3 = DRAM_DRIVE_STRENGTH,
 138        .dram_sdqs4 = DRAM_DRIVE_STRENGTH,
 139        .dram_sdqs5 = DRAM_DRIVE_STRENGTH,
 140        .dram_sdqs6 = DRAM_DRIVE_STRENGTH,
 141        .dram_sdqs7 = DRAM_DRIVE_STRENGTH,
 142
 143        /* DQM[0:7]: Differential input, 40 ohm */
 144        .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 145        .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 146        .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 147        .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 148        .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 149        .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 150        .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 151        .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 152};
 153
 154/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 155static struct mx6sdl_iomux_grp_regs const mx6sdl_grp_ioregs = {
 156        /* DDR3 */
 157        .grp_ddr_type = GRP_DDRTYPE,
 158        /* SDQS[0:7]: Differential input, 40 ohm */
 159        .grp_ddrmode_ctl = DDR_ODT,
 160        /* disable DDR pullups */
 161        .grp_ddrpke = DDR_PKE,
 162        /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 163        .grp_addds = DRAM_DRIVE_STRENGTH,
 164        /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 165        .grp_ctlds = DRAM_DRIVE_STRENGTH,
 166        /* DATA[00:63]: Differential input, 40 ohm */
 167        .grp_ddrmode = DDR_ODT,
 168        .grp_b0ds = DRAM_DRIVE_STRENGTH,
 169        .grp_b1ds = DRAM_DRIVE_STRENGTH,
 170        .grp_b2ds = DRAM_DRIVE_STRENGTH,
 171        .grp_b3ds = DRAM_DRIVE_STRENGTH,
 172        .grp_b4ds = DRAM_DRIVE_STRENGTH,
 173        .grp_b5ds = DRAM_DRIVE_STRENGTH,
 174        .grp_b6ds = DRAM_DRIVE_STRENGTH,
 175        .grp_b7ds = DRAM_DRIVE_STRENGTH,
 176};
 177
 178const struct mx6sl_iomux_ddr_regs mx6sl_ddr_ioregs = {
 179        .dram_sdqs0 = DRAM_DRIVE_STRENGTH,
 180        .dram_sdqs1 = DRAM_DRIVE_STRENGTH,
 181        .dram_sdqs2 = DRAM_DRIVE_STRENGTH,
 182        .dram_sdqs3 = DRAM_DRIVE_STRENGTH,
 183        .dram_dqm0 = DRAM_DRIVE_STRENGTH,
 184        .dram_dqm1 = DRAM_DRIVE_STRENGTH,
 185        .dram_dqm2 = DRAM_DRIVE_STRENGTH,
 186        .dram_dqm3 = DRAM_DRIVE_STRENGTH,
 187        .dram_cas  = DRAM_DRIVE_STRENGTH,
 188        .dram_ras  = DRAM_DRIVE_STRENGTH,
 189        .dram_sdclk_0 = DRAM_DRIVE_STRENGTH,
 190        .dram_reset = DRAM_DRIVE_STRENGTH,
 191        .dram_sdba2 = 0x00020000,
 192        .dram_odt0 = 0x00030000 + DRAM_DRIVE_STRENGTH,
 193        .dram_odt1 = 0x00030000 + DRAM_DRIVE_STRENGTH,
 194};
 195
 196const struct mx6sl_iomux_grp_regs mx6sl_grp_ioregs = {
 197        .grp_b0ds = DRAM_DRIVE_STRENGTH,
 198        .grp_b1ds = DRAM_DRIVE_STRENGTH,
 199        .grp_b2ds = DRAM_DRIVE_STRENGTH,
 200        .grp_b3ds = DRAM_DRIVE_STRENGTH,
 201        .grp_addds = DRAM_DRIVE_STRENGTH,
 202        .grp_ctlds = DRAM_DRIVE_STRENGTH,
 203        .grp_ddrmode_ctl = DDR_ODT,
 204        .grp_ddrpke = DDR_PKE,
 205        .grp_ddrmode = DDR_ODT,
 206        .grp_ddr_type = GRP_DDRTYPE,
 207};
 208
 209static struct mx6_ddr_sysinfo const sysinfo = {
 210        /* width of data bus:0=16,1=32,2=64 */
 211#if CONFIG_DDRWIDTH == 32
 212        .dsize = 1,
 213#elif CONFIG_DDRWIDTH == 64
 214        .dsize = 2,
 215#else
 216#error missing CONFIG_DDRWIDTH
 217#endif
 218        /* config for full 4GB range so that get_mem_size() works */
 219        .cs_density = 32, /* 32Gb per CS */
 220
 221        /* # of chip selects */
 222        .ncs = CONFIG_DDRCS,
 223        .cs1_mirror = 0,
 224        .bi_on = 1,     /* Bank interleaving enabled */
 225        .rtt_nom = CONFIG_RTT_NOM,
 226        .rtt_wr = CONFIG_RTT_WR,
 227        .ralat = CONFIG_RALAT,  /* Read additional latency */
 228        .walat = CONFIG_WALAT,  /* Write additional latency */
 229        .mif3_mode = 3, /* Command prediction working mode */
 230#ifdef CONFIG_DDR3
 231        .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 232        .sde_to_rst = 0x10,     /* JEDEC value for LPDDR2 - 200us */
 233        .pd_fast_exit = 0,      /* immaterial for calibration */
 234        .ddr_type = DDR_TYPE_DDR3,
 235#else
 236        .rst_to_cke = 0x10,     /* JEDEC value for LPDDR2: 200us */
 237        .sde_to_rst = 0,        /* LPDDR2 does not need this field */
 238        .pd_fast_exit = 0,      /* immaterial for calibration */
 239        .ddr_type = DDR_TYPE_LPDDR2,
 240#endif
 241        .refsel = CONFIG_REFSEL,
 242        .refr = CONFIG_REFR,
 243};
 244
 245#ifdef CONFIG_MT41K512M16TNA
 246/* Micron MT41K512M16TNA-125 */
 247static struct mx6_ddr3_cfg const ddrtype = {
 248        .mem_speed = 1600,
 249        .density = 8,
 250        .width = 16,
 251        .banks = 8,
 252        .rowaddr = 15,
 253        .coladdr = 10,
 254        .pagesz = 1,
 255        .trcd = 1375,
 256        .trcmin = 5062,
 257        .trasmin = 3750,
 258};
 259#elif defined(CONFIG_MT41K128M16JT)
 260/* Micron MT41K128M16JT-125 */
 261static struct mx6_ddr3_cfg const ddrtype = {
 262        .mem_speed = 1600,
 263        .density = 2,
 264        .width = 16,
 265        .banks = 8,
 266        .rowaddr = 14,
 267        .coladdr = 10,
 268        .pagesz = 2,
 269        .trcd = 1375,
 270        .trcmin = 4875,
 271        .trasmin = 3500,
 272};
 273#elif defined(CONFIG_H5TQ4G63AFR)
 274/* Hynix H5TQ4G63AFR */
 275static struct mx6_ddr3_cfg const ddrtype = {
 276        .mem_speed = 1600,
 277        .density = 4,
 278        .width = 16,
 279        .banks = 8,
 280        .rowaddr = 15,
 281        .coladdr = 10,
 282        .pagesz = 2,
 283        .trcd = 1375,
 284        .trcmin = 4875,
 285        .trasmin = 3500,
 286};
 287#elif defined CONFIG_H5TQ2G63DFR
 288/* Hynix H5TQ2G63DFR */
 289static struct mx6_ddr3_cfg const ddrtype = {
 290        .mem_speed = 1333,
 291        .density = 2,
 292        .width = 16,
 293        .banks = 8,
 294        .rowaddr = 14,
 295        .coladdr = 10,
 296        .pagesz = 2,
 297        .trcd = 1350,
 298        .trcmin = 4950,
 299        .trasmin = 3600,
 300};
 301#elif defined(CONFIG_MT42L256M32D2LG)
 302/* Micron MT42L256M32D2LG */
 303static struct mx6_lpddr2_cfg ddrtype = {
 304        .mem_speed = 800,
 305        .density = 4,
 306        .width = 32,
 307        .banks = 8,
 308        .rowaddr = 14,
 309        .coladdr = 10,
 310        .trcd_lp = 2000,
 311        .trppb_lp = 2000,
 312        .trpab_lp = 2250,
 313        .trasmin = 4200,
 314};
 315#elif defined(CONFIG_MT29PZZZ4D4BKESK)
 316/* Micron MT29PZZZ4D4BKESK */
 317static struct mx6_lpddr2_cfg ddrtype = {
 318        .mem_speed = 800,
 319        .density = 4,
 320        .width = 32,
 321        .banks = 8,
 322        .rowaddr = 14,
 323        .coladdr = 10,
 324        .trcd_lp = 2000,
 325        .trppb_lp = 2000,
 326        .trpab_lp = 2250,
 327        .trasmin = 4200,
 328};
 329#else
 330#error please select DDR type using menuconfig
 331#endif
 332
 333static void ccgr_init(void)
 334{
 335        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 336
 337        /* FIXME: these should probably be checked, especially
 338         * for i.MX6SL, UL, ULL
 339         */
 340        writel(0x00C03F3F, &ccm->CCGR0);
 341        writel(0x0030FC03, &ccm->CCGR1);
 342        writel(0x0FFFC000, &ccm->CCGR2);
 343        writel(0x3FF00000, &ccm->CCGR3);
 344        writel(0x00FFF300, &ccm->CCGR4);
 345        writel(0x0F0000C3, &ccm->CCGR5);
 346        writel(0x000003FF, &ccm->CCGR6);
 347}
 348
 349static void display_calibration(struct mx6_mmdc_calibration *calib)
 350{
 351        printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0);
 352        printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1);
 353        printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl);
 354        printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl);
 355        printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0);
 356        printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1);
 357        if (sysinfo.dsize == 2) {
 358                printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0);
 359                printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1);
 360                printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl);
 361                printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl);
 362                printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0);
 363                printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1);
 364        }
 365#ifdef CONFIG_IMXIMAGE_OUTPUT
 366        printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0);
 367        printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1);
 368        printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl);
 369        printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl);
 370        printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n",
 371               calib->p0_mpwldectrl0);
 372        printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n",
 373               calib->p0_mpwldectrl1);
 374        if (sysinfo.dsize == 2) {
 375                printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n",
 376                       calib->p1_mpdgctrl0);
 377                printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n",
 378                       calib->p1_mpdgctrl1);
 379                printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n",
 380                       calib->p1_mprddlctl);
 381                printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n",
 382                       calib->p1_mpwrdlctl);
 383                printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n",
 384                       calib->p1_mpwldectrl0);
 385                printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n",
 386                       calib->p1_mpwldectrl1);
 387        }
 388#endif
 389}
 390
 391/*
 392 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 393 * - we have a stack and a place to store GD, both in SRAM
 394 * - no variable global data is available
 395 */
 396void board_init_f(ulong dummy)
 397{
 398        int errs;
 399        struct mx6_mmdc_calibration calibration = {0};
 400
 401        memset((void *)gd, 0, sizeof(struct global_data));
 402
 403        /* write leveling calibration defaults */
 404        calibration.p0_mpwrdlctl = 0x40404040;
 405        calibration.p1_mpwrdlctl = 0x40404040;
 406
 407        /* setup AIPS and disable watchdog */
 408        arch_cpu_init();
 409
 410        ccgr_init();
 411
 412        SETUP_IOMUX_PADS(uart_pads);
 413
 414        /* setup GP timer */
 415        timer_init();
 416
 417        /* UART clocks enabled and gd valid - init serial console */
 418        preloader_console_init();
 419
 420        if (sysinfo.dsize != 1) {
 421                if (is_cpu_type(MXC_CPU_MX6SX) ||
 422                    is_cpu_type(MXC_CPU_MX6UL) ||
 423                    is_cpu_type(MXC_CPU_MX6ULL) ||
 424                    is_cpu_type(MXC_CPU_MX6SL)) {
 425                        printf("cpu type 0x%x doesn't support 64-bit bus\n",
 426                               get_cpu_type());
 427                        reset_cpu(0);
 428                }
 429        }
 430#ifdef CONFIG_MX6SL
 431        mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs,
 432                         &mx6sl_grp_ioregs);
 433#else
 434        if (is_cpu_type(MXC_CPU_MX6Q)) {
 435                mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs,
 436                                 &mx6dq_grp_ioregs);
 437        } else {
 438                mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs,
 439                                  &mx6sdl_grp_ioregs);
 440        }
 441#endif
 442        mx6_dram_cfg(&sysinfo, &calibration, &ddrtype);
 443
 444        errs = mmdc_do_write_level_calibration(&sysinfo);
 445        if (errs) {
 446                printf("error %d from write level calibration\n", errs);
 447        } else {
 448                errs = mmdc_do_dqs_calibration(&sysinfo);
 449                if (errs) {
 450                        printf("error %d from dqs calibration\n", errs);
 451                } else {
 452                        printf("completed successfully\n");
 453                        mmdc_read_calibration(&sysinfo, &calibration);
 454                        display_calibration(&calibration);
 455                }
 456        }
 457}
 458