LXR uboot/board/freescale/t104xrdb/spl.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/* Copyright 2013 Freescale Semiconductor, Inc.
   3 */
   4
   5#include <common.h>
   6#include <clock_legacy.h>
   7#include <console.h>
   8#include <env_internal.h>
   9#include <init.h>
  10#include <malloc.h>
  11#include <ns16550.h>
  12#include <nand.h>
  13#include <i2c.h>
  14#include <mmc.h>
  15#include <fsl_esdhc.h>
  16#include <spi_flash.h>
  17#include "../common/sleep.h"
  18#include "../common/spl.h"
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22phys_size_t get_effective_memsize(void)
  23{
  24        return CONFIG_SYS_L3_SIZE;
  25}
  26
  27unsigned long get_board_sys_clk(void)
  28{
  29        return CONFIG_SYS_CLK_FREQ;
  30}
  31
  32unsigned long get_board_ddr_clk(void)
  33{
  34        return CONFIG_DDR_CLK_FREQ;
  35}
  36
  37#define FSL_CORENET_CCSR_PORSR1_RCW_MASK        0xFF800000
  38void board_init_f(ulong bootflag)
  39{
  40        u32 plat_ratio, sys_clk, uart_clk;
  41#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
  42        u32 porsr1, pinctl;
  43        u32 svr = get_svr();
  44#endif
  45        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  46
  47#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
  48        if (IS_SVR_REV(svr, 1, 0)) {
  49                /*
  50                 * There is T1040 SoC issue where NOR, FPGA are inaccessible
  51                 * during NAND boot because IFC signals > IFC_AD7 are not
  52                 * enabled. This workaround changes RCW source to make all
  53                 * signals enabled.
  54                 */
  55                porsr1 = in_be32(&gur->porsr1);
  56                pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
  57                          | 0x24800000);
  58                out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
  59                         pinctl);
  60        }
  61#endif
  62
  63        /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  64        memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  65
  66        /* Update GD pointer */
  67        gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  68
  69#ifdef CONFIG_DEEP_SLEEP
  70        /* disable the console if boot from deep sleep */
  71        if (is_warm_boot())
  72                fsl_dp_disable_console();
  73#endif
  74        /* compiler optimization barrier needed for GCC >= 3.4 */
  75        __asm__ __volatile__("" : : : "memory");
  76
  77        console_init_f();
  78
  79        /* initialize selected port with appropriate baud rate */
  80        sys_clk = get_board_sys_clk();
  81        plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  82        uart_clk = sys_clk * plat_ratio / 2;
  83
  84        NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  85                     uart_clk / 16 / CONFIG_BAUDRATE);
  86
  87        relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  88}
  89
  90void board_init_r(gd_t *gd, ulong dest_addr)
  91{
  92        struct bd_info *bd;
  93
  94        bd = (struct bd_info *)(gd + sizeof(gd_t));
  95        memset(bd, 0, sizeof(struct bd_info));
  96        gd->bd = bd;
  97
  98        arch_cpu_init();
  99        get_clocks();
 100        mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 101                        CONFIG_SPL_RELOC_MALLOC_SIZE);
 102        gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 103
 104#ifdef CONFIG_SPL_MMC_BOOT
 105        mmc_initialize(bd);
 106#endif
 107
 108        /* relocate environment function pointers etc. */
 109#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
 110        defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 111#ifdef CONFIG_SPL_NAND_BOOT
 112        nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 113                            (uchar *)SPL_ENV_ADDR);
 114#endif
 115#ifdef CONFIG_SPL_MMC_BOOT
 116        mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 117                           (uchar *)SPL_ENV_ADDR);
 118#endif
 119#ifdef CONFIG_SPL_SPI_BOOT
 120        fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 121                               (uchar *)SPL_ENV_ADDR);
 122#endif
 123        gd->env_addr  = (ulong)(SPL_ENV_ADDR);
 124        gd->env_valid = ENV_VALID;
 125#endif
 126
 127        i2c_init_all();
 128
 129        puts("\n\n");
 130
 131        dram_init();
 132
 133#ifdef CONFIG_SPL_MMC_BOOT
 134        mmc_boot();
 135#elif defined(CONFIG_SPL_SPI_BOOT)
 136        fsl_spi_boot();
 137#elif defined(CONFIG_SPL_NAND_BOOT)
 138        nand_boot();
 139#endif
 140}
 141