1
2
3
4
5
6#include <common.h>
7#include <ahci.h>
8#include <cpu_func.h>
9#include <env.h>
10#include <fdt_support.h>
11#include <init.h>
12#include <net.h>
13#include <netdev.h>
14#include <scsi.h>
15
16#include <linux/sizes.h>
17#include <asm/io.h>
18
19#define HB_AHCI_BASE 0xffe08000
20
21#define HB_SCU_A9_PWR_STATUS 0xfff10008
22#define HB_SREG_A9_PWR_REQ 0xfff3cf00
23#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
24#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
25#define HB_SREG_A15_PWR_CTRL 0xfff3c200
26
27#define HB_PWR_SUSPEND 0
28#define HB_PWR_SOFT_RESET 1
29#define HB_PWR_HARD_RESET 2
30#define HB_PWR_SHUTDOWN 3
31
32#define PWRDOM_STAT_SATA 0x80000000
33#define PWRDOM_STAT_PCI 0x40000000
34#define PWRDOM_STAT_EMMC 0x20000000
35
36#define HB_SCU_A9_PWR_NORMAL 0
37#define HB_SCU_A9_PWR_DORMANT 2
38#define HB_SCU_A9_PWR_OFF 3
39
40DECLARE_GLOBAL_DATA_PTR;
41
42void cphy_disable_overrides(void);
43
44
45
46
47int board_init(void)
48{
49 icache_enable();
50
51 return 0;
52}
53
54
55int board_eth_init(struct bd_info *bis)
56{
57 int rc = 0;
58
59#ifdef CONFIG_CALXEDA_XGMAC
60 rc += calxedaxgmac_initialize(0, 0xfff50000);
61 rc += calxedaxgmac_initialize(1, 0xfff51000);
62#endif
63 return rc;
64}
65
66#ifdef CONFIG_SCSI_AHCI_PLAT
67void scsi_init(void)
68{
69 u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
70
71 cphy_disable_overrides();
72 if (reg & PWRDOM_STAT_SATA) {
73 ahci_init((void __iomem *)HB_AHCI_BASE);
74 scsi_scan(true);
75 }
76}
77#endif
78
79#ifdef CONFIG_MISC_INIT_R
80int misc_init_r(void)
81{
82 char envbuffer[16];
83 u32 boot_choice;
84
85 boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
86 sprintf(envbuffer, "bootcmd%d", boot_choice);
87 if (env_get(envbuffer)) {
88 sprintf(envbuffer, "run bootcmd%d", boot_choice);
89 env_set("bootcmd", envbuffer);
90 } else
91 env_set("bootcmd", "");
92
93 return 0;
94}
95#endif
96
97int dram_init(void)
98{
99 gd->ram_size = SZ_512M;
100 return 0;
101}
102
103#if defined(CONFIG_OF_BOARD_SETUP)
104int ft_board_setup(void *fdt, struct bd_info *bd)
105{
106 static const char disabled[] = "disabled";
107 u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
108
109 if (!(reg & PWRDOM_STAT_SATA))
110 do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
111 disabled, sizeof(disabled), 1);
112
113 if (!(reg & PWRDOM_STAT_EMMC))
114 do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
115 disabled, sizeof(disabled), 1);
116
117 return 0;
118}
119#endif
120
121static int is_highbank(void)
122{
123 uint32_t midr;
124
125 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
126
127 return (midr & 0xfff0) == 0xc090;
128}
129
130void reset_cpu(ulong addr)
131{
132 writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
133 if (is_highbank())
134 writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
135 else
136 writel(0x1, HB_SREG_A15_PWR_CTRL);
137
138 wfi();
139}
140
141
142
143
144
145void arch_preboot_os(void)
146{
147 cphy_disable_overrides();
148}
149