1
2
3
4
5#include <common.h>
6#include <init.h>
7#include <asm/io.h>
8#include <asm/arch/at91_sfr.h>
9#include <asm/arch/sama5d3_smc.h>
10#include <asm/arch/at91_common.h>
11#include <asm/arch/at91_pmc.h>
12#include <asm/arch/at91_rstc.h>
13#include <asm/arch/gpio.h>
14#include <asm/arch/clk.h>
15#include <env.h>
16#include <micrel.h>
17#include <net.h>
18#include <netdev.h>
19#include <spl.h>
20#include <asm/arch/atmel_mpddrc.h>
21#include <asm/arch/at91_wdt.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
25
26
27
28
29
30void wb50n_nand_hw_init(void)
31{
32 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
33
34 at91_periph_clk_enable(ATMEL_ID_SMC);
35
36
37 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
38 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
39 &smc->cs[3].setup);
40 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
41 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
42 &smc->cs[3].pulse);
43 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
44 &smc->cs[3].cycle);
45 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
46 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
47 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) |
48 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
49 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
50 AT91_SMC_MODE_EXNW_DISABLE |
51 AT91_SMC_MODE_DBW_8 |
52 AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);
53
54
55 at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
56}
57
58int board_early_init_f(void)
59{
60 at91_periph_clk_enable(ATMEL_ID_PIOA);
61 at91_periph_clk_enable(ATMEL_ID_PIOB);
62 at91_periph_clk_enable(ATMEL_ID_PIOC);
63 at91_periph_clk_enable(ATMEL_ID_PIOD);
64 at91_periph_clk_enable(ATMEL_ID_PIOE);
65
66 at91_seriald_hw_init();
67
68 return 0;
69}
70
71int board_init(void)
72{
73
74 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
75
76 wb50n_nand_hw_init();
77
78 at91_macb_hw_init();
79
80 return 0;
81}
82
83int dram_init(void)
84{
85 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
86 CONFIG_SYS_SDRAM_SIZE);
87 return 0;
88}
89
90int board_phy_config(struct phy_device *phydev)
91{
92
93 ksz9021_phy_extended_write(phydev,
94 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
95
96 ksz9021_phy_extended_write(phydev,
97 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
98
99 ksz9021_phy_extended_write(phydev,
100 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
101
102 return 0;
103}
104
105int board_eth_init(struct bd_info *bis)
106{
107 int rc = 0;
108
109 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
110
111 return rc;
112}
113
114#ifdef CONFIG_BOARD_LATE_INIT
115#include <linux/ctype.h>
116int board_late_init(void)
117{
118#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
119 const char *LAIRD_NAME = "lrd_name";
120 char name[32], *p;
121
122 strcpy(name, get_cpu_name());
123 for (p = name; *p != '\0'; *p = tolower(*p), p++)
124 ;
125 strcat(name, "-wb50n");
126 env_set(LAIRD_NAME, name);
127
128#endif
129
130 return 0;
131}
132#endif
133
134
135#ifdef CONFIG_SPL_BUILD
136void spl_board_init(void)
137{
138 wb50n_nand_hw_init();
139}
140
141static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
142{
143 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
144
145 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
146 ATMEL_MPDDRC_CR_NR_ROW_13 |
147 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
148 ATMEL_MPDDRC_CR_NDQS_DISABLED |
149 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
150 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
151
152 ddr2->rtr = 0x411;
153
154 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
155 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
156 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
157 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
158 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
159 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
160 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
161 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
162
163 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
164 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
165 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
166 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
167
168 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
169 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
170 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
171 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
172 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
173}
174
175void mem_init(void)
176{
177 struct atmel_mpddrc_config ddr2;
178
179 ddr2_conf(&ddr2);
180
181 configure_ddrcfg_input_buffers(true);
182
183
184 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
185 at91_system_clk_enable(AT91_PMC_DDR);
186
187
188 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
189}
190
191void at91_pmc_init(void)
192{
193 u32 tmp;
194
195 tmp = AT91_PMC_PLLAR_29 |
196 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
197 AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1);
198 at91_plla_init(tmp);
199
200 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
201
202 tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA;
203 at91_mck_init(tmp);
204}
205#endif
206
