LXR uboot/board/myir/mys_6ulx/mys

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2020 Linumiz
   4 * Author: Parthiban Nallathambi <parthiban@linumiz.com>
   5 */
   6
   7#include <init.h>
   8#include <asm/arch/clock.h>
   9#include <asm/arch/crm_regs.h>
  10#include <asm/arch/mx6-pins.h>
  11#include <asm/arch/sys_proto.h>
  12#include <asm/mach-imx/iomux-v3.h>
  13#include <asm/mach-imx/mxc_i2c.h>
  14#include <fsl_esdhc_imx.h>
  15#include <linux/bitops.h>
  16#include <miiphy.h>
  17#include <netdev.h>
  18#include <usb.h>
  19#include <usb/ehci-ci.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23int dram_init(void)
  24{
  25        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  26
  27        return 0;
  28}
  29
  30#define UART_PAD_CTRL  (PAD_CTL_PKE         | PAD_CTL_PUE       | \
  31                        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  32                        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | \
  33                        PAD_CTL_HYS)
  34
  35static iomux_v3_cfg_t const uart1_pads[] = {
  36        MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  37        MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  38};
  39
  40static iomux_v3_cfg_t const uart5_pads[] = {
  41        MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  42        MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  43        MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  44        MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  45};
  46
  47static void setup_iomux_uart(void)
  48{
  49        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  50        imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  51}
  52
  53#ifdef CONFIG_FEC_MXC
  54
  55static int setup_fec(void)
  56{
  57        struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  58        int ret;
  59
  60        /*
  61         * Use 50M anatop loopback REF_CLK1 for ENET1,
  62         * clear gpr1[13], set gpr1[17].
  63         */
  64        clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  65                        IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  66
  67        ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  68        if (ret)
  69                return ret;
  70
  71        enable_enet_clk(1);
  72
  73        return 0;
  74}
  75
  76int board_phy_config(struct phy_device *phydev)
  77{
  78        /*
  79         * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
  80         * 50 MHz RMII clock mode.
  81         */
  82        phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  83
  84        if (phydev->drv->config)
  85                phydev->drv->config(phydev);
  86
  87        return 0;
  88}
  89#endif /* CONFIG_FEC_MXC */
  90
  91int board_early_init_f(void)
  92{
  93        setup_iomux_uart();
  94
  95        return 0;
  96}
  97
  98int board_init(void)
  99{
 100        /* Address of boot parameters */
 101        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 102
 103#ifdef CONFIG_FEC_MXC
 104        setup_fec();
 105#endif
 106        return 0;
 107}
 108
 109int checkboard(void)
 110{
 111        u32 cpurev = get_cpu_rev();
 112
 113        printf("Board: MYiR MYS-6ULX %s Single Board Computer\n",
 114               get_imx_type((cpurev & 0xFF000) >> 12));
 115
 116        return 0;
 117}
 118