uboot/drivers/ddr/fsl/ctrl_regs.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
   4 * Copyright 2017-2020 NXP Semiconductor
   5 */
   6
   7/*
   8 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
   9 * Based on code from spd_sdram.c
  10 * Author: James Yang [at freescale.com]
  11 */
  12
  13#include <common.h>
  14#include <fsl_ddr_sdram.h>
  15#include <fsl_errata.h>
  16#include <fsl_ddr.h>
  17#include <fsl_immap.h>
  18#include <log.h>
  19#include <asm/bitops.h>
  20#include <asm/io.h>
  21#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  22        defined(CONFIG_ARM)
  23#include <asm/arch/clock.h>
  24#endif
  25
  26/*
  27 * Determine Rtt value.
  28 *
  29 * This should likely be either board or controller specific.
  30 *
  31 * Rtt(nominal) - DDR2:
  32 *      0 = Rtt disabled
  33 *      1 = 75 ohm
  34 *      2 = 150 ohm
  35 *      3 = 50 ohm
  36 * Rtt(nominal) - DDR3:
  37 *      0 = Rtt disabled
  38 *      1 = 60 ohm
  39 *      2 = 120 ohm
  40 *      3 = 40 ohm
  41 *      4 = 20 ohm
  42 *      5 = 30 ohm
  43 *
  44 * FIXME: Apparently 8641 needs a value of 2
  45 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  46 *
  47 * FIXME: There was some effort down this line earlier:
  48 *
  49 *      unsigned int i;
  50 *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  51 *              if (popts->dimmslot[i].num_valid_cs
  52 *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  53 *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  54 *                      rtt = 2;
  55 *                      break;
  56 *              }
  57 *      }
  58 */
  59static inline int fsl_ddr_get_rtt(void)
  60{
  61        int rtt;
  62
  63#if defined(CONFIG_SYS_FSL_DDR1)
  64        rtt = 0;
  65#elif defined(CONFIG_SYS_FSL_DDR2)
  66        rtt = 3;
  67#else
  68        rtt = 0;
  69#endif
  70
  71        return rtt;
  72}
  73
  74#ifdef CONFIG_SYS_FSL_DDR4
  75/*
  76 * compute CAS write latency according to DDR4 spec
  77 * CWL = 9 for <= 1600MT/s
  78 *       10 for <= 1866MT/s
  79 *       11 for <= 2133MT/s
  80 *       12 for <= 2400MT/s
  81 *       14 for <= 2667MT/s
  82 *       16 for <= 2933MT/s
  83 *       18 for higher
  84 */
  85static inline unsigned int compute_cas_write_latency(
  86                                const unsigned int ctrl_num)
  87{
  88        unsigned int cwl;
  89        const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  90        if (mclk_ps >= 1250)
  91                cwl = 9;
  92        else if (mclk_ps >= 1070)
  93                cwl = 10;
  94        else if (mclk_ps >= 935)
  95                cwl = 11;
  96        else if (mclk_ps >= 833)
  97                cwl = 12;
  98        else if (mclk_ps >= 750)
  99                cwl = 14;
 100        else if (mclk_ps >= 681)
 101                cwl = 16;
 102        else
 103                cwl = 18;
 104
 105        return cwl;
 106}
 107#else
 108/*
 109 * compute the CAS write latency according to DDR3 spec
 110 * CWL = 5 if tCK >= 2.5ns
 111 *       6 if 2.5ns > tCK >= 1.875ns
 112 *       7 if 1.875ns > tCK >= 1.5ns
 113 *       8 if 1.5ns > tCK >= 1.25ns
 114 *       9 if 1.25ns > tCK >= 1.07ns
 115 *       10 if 1.07ns > tCK >= 0.935ns
 116 *       11 if 0.935ns > tCK >= 0.833ns
 117 *       12 if 0.833ns > tCK >= 0.75ns
 118 */
 119static inline unsigned int compute_cas_write_latency(
 120                                const unsigned int ctrl_num)
 121{
 122        unsigned int cwl;
 123        const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 124
 125        if (mclk_ps >= 2500)
 126                cwl = 5;
 127        else if (mclk_ps >= 1875)
 128                cwl = 6;
 129        else if (mclk_ps >= 1500)
 130                cwl = 7;
 131        else if (mclk_ps >= 1250)
 132                cwl = 8;
 133        else if (mclk_ps >= 1070)
 134                cwl = 9;
 135        else if (mclk_ps >= 935)
 136                cwl = 10;
 137        else if (mclk_ps >= 833)
 138                cwl = 11;
 139        else if (mclk_ps >= 750)
 140                cwl = 12;
 141        else {
 142                cwl = 12;
 143                printf("Warning: CWL is out of range\n");
 144        }
 145        return cwl;
 146}
 147#endif
 148
 149/* Chip Select Configuration (CSn_CONFIG) */
 150static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 151                               const memctl_options_t *popts,
 152                               const dimm_params_t *dimm_params)
 153{
 154        unsigned int cs_n_en = 0; /* Chip Select enable */
 155        unsigned int intlv_en = 0; /* Memory controller interleave enable */
 156        unsigned int intlv_ctl = 0; /* Interleaving control */
 157        unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 158        unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 159        unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 160        unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 161        unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 162        unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 163        int go_config = 0;
 164#ifdef CONFIG_SYS_FSL_DDR4
 165        unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 166#else
 167        unsigned int n_banks_per_sdram_device;
 168#endif
 169
 170        /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 171        switch (i) {
 172        case 0:
 173                if (dimm_params[dimm_number].n_ranks > 0) {
 174                        go_config = 1;
 175                        /* These fields only available in CS0_CONFIG */
 176                        if (!popts->memctl_interleaving)
 177                                break;
 178                        switch (popts->memctl_interleaving_mode) {
 179                        case FSL_DDR_256B_INTERLEAVING:
 180                        case FSL_DDR_CACHE_LINE_INTERLEAVING:
 181                        case FSL_DDR_PAGE_INTERLEAVING:
 182                        case FSL_DDR_BANK_INTERLEAVING:
 183                        case FSL_DDR_SUPERBANK_INTERLEAVING:
 184                                intlv_en = popts->memctl_interleaving;
 185                                intlv_ctl = popts->memctl_interleaving_mode;
 186                                break;
 187                        default:
 188                                break;
 189                        }
 190                }
 191                break;
 192        case 1:
 193                if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 194                    (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 195                        go_config = 1;
 196                break;
 197        case 2:
 198                if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 199                   (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 200                        go_config = 1;
 201                break;
 202        case 3:
 203                if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 204                    (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 205                    (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 206                        go_config = 1;
 207                break;
 208        default:
 209                break;
 210        }
 211        if (go_config) {
 212                cs_n_en = 1;
 213                ap_n_en = popts->cs_local_opts[i].auto_precharge;
 214                odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 215                odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 216#ifdef CONFIG_SYS_FSL_DDR4
 217                ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 218                bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 219#else
 220                n_banks_per_sdram_device
 221                        = dimm_params[dimm_number].n_banks_per_sdram_device;
 222                ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 223#endif
 224                row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 225                col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 226        }
 227        ddr->cs[i].config = (0
 228                | ((cs_n_en & 0x1) << 31)
 229                | ((intlv_en & 0x3) << 29)
 230                | ((intlv_ctl & 0xf) << 24)
 231                | ((ap_n_en & 0x1) << 23)
 232
 233                /* XXX: some implementation only have 1 bit starting at left */
 234                | ((odt_rd_cfg & 0x7) << 20)
 235
 236                /* XXX: Some implementation only have 1 bit starting at left */
 237                | ((odt_wr_cfg & 0x7) << 16)
 238
 239                | ((ba_bits_cs_n & 0x3) << 14)
 240                | ((row_bits_cs_n & 0x7) << 8)
 241#ifdef CONFIG_SYS_FSL_DDR4
 242                | ((bg_bits_cs_n & 0x3) << 4)
 243#endif
 244                | ((col_bits_cs_n & 0x7) << 0)
 245                );
 246        debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 247}
 248
 249/* Chip Select Configuration 2 (CSn_CONFIG_2) */
 250/* FIXME: 8572 */
 251static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 252{
 253        unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 254
 255        ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 256        debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 257}
 258
 259/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 260
 261#if !defined(CONFIG_SYS_FSL_DDR1)
 262/*
 263 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
 264 * Return 1 if other two slots configuration. Return 0 if single slot.
 265 */
 266static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 267{
 268#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 269        if (dimm_params[0].n_ranks == 4)
 270                return 2;
 271#endif
 272
 273#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 274        if ((dimm_params[0].n_ranks == 2) &&
 275                (dimm_params[1].n_ranks == 2))
 276                return 2;
 277
 278#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 279        if (dimm_params[0].n_ranks == 4)
 280                return 2;
 281#endif
 282
 283        if ((dimm_params[0].n_ranks != 0) &&
 284            (dimm_params[2].n_ranks != 0))
 285                return 1;
 286#endif
 287        return 0;
 288}
 289
 290/*
 291 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 292 *
 293 * Avoid writing for DDR I.  The new PQ38 DDR controller
 294 * dreams up non-zero default values to be backwards compatible.
 295 */
 296static void set_timing_cfg_0(const unsigned int ctrl_num,
 297                                fsl_ddr_cfg_regs_t *ddr,
 298                                const memctl_options_t *popts,
 299                                const dimm_params_t *dimm_params)
 300{
 301        unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 302        unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 303        /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 304        unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 305        unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 306
 307        /* Active powerdown exit timing (tXARD and tXARDS). */
 308        unsigned char act_pd_exit_mclk;
 309        /* Precharge powerdown exit timing (tXP). */
 310        unsigned char pre_pd_exit_mclk;
 311        /* ODT powerdown exit timing (tAXPD). */
 312        unsigned char taxpd_mclk = 0;
 313        /* Mode register set cycle time (tMRD). */
 314        unsigned char tmrd_mclk;
 315#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 316        const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 317#endif
 318
 319#ifdef CONFIG_SYS_FSL_DDR4
 320        /* tXP=max(4nCK, 6ns) */
 321        int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 322        unsigned int data_rate = get_ddr_freq(ctrl_num);
 323
 324        /* for faster clock, need more time for data setup */
 325        trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
 326
 327        /*
 328         * for single quad-rank DIMM and two-slot DIMMs
 329         * to avoid ODT overlap
 330         */
 331        switch (avoid_odt_overlap(dimm_params)) {
 332        case 2:
 333                twrt_mclk = 2;
 334                twwt_mclk = 2;
 335                trrt_mclk = 2;
 336                break;
 337        default:
 338                twrt_mclk = 1;
 339                twwt_mclk = 1;
 340                trrt_mclk = 0;
 341                break;
 342        }
 343
 344        act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 345        pre_pd_exit_mclk = act_pd_exit_mclk;
 346        /*
 347         * MRS_CYC = max(tMRD, tMOD)
 348         * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 349         */
 350        tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 351#elif defined(CONFIG_SYS_FSL_DDR3)
 352        unsigned int data_rate = get_ddr_freq(ctrl_num);
 353        int txp;
 354        unsigned int ip_rev;
 355        int odt_overlap;
 356        /*
 357         * (tXARD and tXARDS). Empirical?
 358         * The DDR3 spec has not tXARD,
 359         * we use the tXP instead of it.
 360         * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
 361         *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 362         * spec has not the tAXPD, we use
 363         * tAXPD=1, need design to confirm.
 364         */
 365        txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 366
 367        ip_rev = fsl_ddr_get_version(ctrl_num);
 368        if (ip_rev >= 0x40700) {
 369                /*
 370                 * MRS_CYC = max(tMRD, tMOD)
 371                 * tMRD = 4nCK (8nCK for RDIMM)
 372                 * tMOD = max(12nCK, 15ns)
 373                 */
 374                tmrd_mclk = max((unsigned int)12,
 375                                picos_to_mclk(ctrl_num, 15000));
 376        } else {
 377                /*
 378                 * MRS_CYC = tMRD
 379                 * tMRD = 4nCK (8nCK for RDIMM)
 380                 */
 381                if (popts->registered_dimm_en)
 382                        tmrd_mclk = 8;
 383                else
 384                        tmrd_mclk = 4;
 385        }
 386
 387        /* set the turnaround time */
 388
 389        /*
 390         * for single quad-rank DIMM and two-slot DIMMs
 391         * to avoid ODT overlap
 392         */
 393        odt_overlap = avoid_odt_overlap(dimm_params);
 394        switch (odt_overlap) {
 395        case 2:
 396                twwt_mclk = 2;
 397                trrt_mclk = 1;
 398                break;
 399        case 1:
 400                twwt_mclk = 1;
 401                trrt_mclk = 0;
 402                break;
 403        default:
 404                break;
 405        }
 406
 407        /* for faster clock, need more time for data setup */
 408        trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 409
 410        if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 411                twrt_mclk = 1;
 412
 413        if (popts->dynamic_power == 0) {        /* powerdown is not used */
 414                act_pd_exit_mclk = 1;
 415                pre_pd_exit_mclk = 1;
 416                taxpd_mclk = 1;
 417        } else {
 418                /* act_pd_exit_mclk = tXARD, see above */
 419                act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 420                /* Mode register MR0[A12] is '1' - fast exit */
 421                pre_pd_exit_mclk = act_pd_exit_mclk;
 422                taxpd_mclk = 1;
 423        }
 424#else /* CONFIG_SYS_FSL_DDR2 */
 425        /*
 426         * (tXARD and tXARDS). Empirical?
 427         * tXARD = 2 for DDR2
 428         * tXP=2
 429         * tAXPD=8
 430         */
 431        act_pd_exit_mclk = 2;
 432        pre_pd_exit_mclk = 2;
 433        taxpd_mclk = 8;
 434        tmrd_mclk = 2;
 435#endif
 436
 437        if (popts->trwt_override)
 438                trwt_mclk = popts->trwt;
 439
 440        ddr->timing_cfg_0 = (0
 441                | ((trwt_mclk & 0x3) << 30)     /* RWT */
 442                | ((twrt_mclk & 0x3) << 28)     /* WRT */
 443                | ((trrt_mclk & 0x3) << 26)     /* RRT */
 444                | ((twwt_mclk & 0x3) << 24)     /* WWT */
 445                | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 446                | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 447                | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 448                | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 449                );
 450        debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 451}
 452#endif  /* !defined(CONFIG_SYS_FSL_DDR1) */
 453
 454/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 455static void set_timing_cfg_3(const unsigned int ctrl_num,
 456                             fsl_ddr_cfg_regs_t *ddr,
 457                             const memctl_options_t *popts,
 458                             const common_timing_params_t *common_dimm,
 459                             unsigned int cas_latency,
 460                             unsigned int additive_latency)
 461{
 462        /* Extended precharge to activate interval (tRP) */
 463        unsigned int ext_pretoact = 0;
 464        /* Extended Activate to precharge interval (tRAS) */
 465        unsigned int ext_acttopre = 0;
 466        /* Extended activate to read/write interval (tRCD) */
 467        unsigned int ext_acttorw = 0;
 468        /* Extended refresh recovery time (tRFC) */
 469        unsigned int ext_refrec;
 470        /* Extended MCAS latency from READ cmd */
 471        unsigned int ext_caslat = 0;
 472        /* Extended additive latency */
 473        unsigned int ext_add_lat = 0;
 474        /* Extended last data to precharge interval (tWR) */
 475        unsigned int ext_wrrec = 0;
 476        /* Control Adjust */
 477        unsigned int cntl_adj = 0;
 478
 479        ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
 480        ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
 481        ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 482        ext_caslat = (2 * cas_latency - 1) >> 4;
 483        ext_add_lat = additive_latency >> 4;
 484#ifdef CONFIG_SYS_FSL_DDR4
 485        ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 486#else
 487        ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 488        /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 489#endif
 490        ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 491                (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 492
 493        ddr->timing_cfg_3 = (0
 494                | ((ext_pretoact & 0x1) << 28)
 495                | ((ext_acttopre & 0x3) << 24)
 496                | ((ext_acttorw & 0x1) << 22)
 497                | ((ext_refrec & 0x3F) << 16)
 498                | ((ext_caslat & 0x3) << 12)
 499                | ((ext_add_lat & 0x1) << 10)
 500                | ((ext_wrrec & 0x1) << 8)
 501                | ((cntl_adj & 0x7) << 0)
 502                );
 503        debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 504}
 505
 506/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 507static void set_timing_cfg_1(const unsigned int ctrl_num,
 508                             fsl_ddr_cfg_regs_t *ddr,
 509                             const memctl_options_t *popts,
 510                             const common_timing_params_t *common_dimm,
 511                             unsigned int cas_latency)
 512{
 513        /* Precharge-to-activate interval (tRP) */
 514        unsigned char pretoact_mclk;
 515        /* Activate to precharge interval (tRAS) */
 516        unsigned char acttopre_mclk;
 517        /*  Activate to read/write interval (tRCD) */
 518        unsigned char acttorw_mclk;
 519        /* CASLAT */
 520        unsigned char caslat_ctrl;
 521        /*  Refresh recovery time (tRFC) ; trfc_low */
 522        unsigned char refrec_ctrl;
 523        /* Last data to precharge minimum interval (tWR) */
 524        unsigned char wrrec_mclk;
 525        /* Activate-to-activate interval (tRRD) */
 526        unsigned char acttoact_mclk;
 527        /* Last write data pair to read command issue interval (tWTR) */
 528        unsigned char wrtord_mclk;
 529#ifdef CONFIG_SYS_FSL_DDR4
 530        /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 531        static const u8 wrrec_table[] = {
 532                10, 10, 10, 10, 10,
 533                10, 10, 10, 10, 10,
 534                12, 12, 14, 14, 16,
 535                16, 18, 18, 20, 20,
 536                24, 24, 24, 24};
 537#else
 538        /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 539        static const u8 wrrec_table[] = {
 540                1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 541#endif
 542
 543        pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
 544        acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
 545        acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 546
 547        /*
 548         * Translate CAS Latency to a DDR controller field value:
 549         *
 550         *      CAS Lat DDR I   DDR II  Ctrl
 551         *      Clocks  SPD Bit SPD Bit Value
 552         *      ------- ------- ------- -----
 553         *      1.0     0               0001
 554         *      1.5     1               0010
 555         *      2.0     2       2       0011
 556         *      2.5     3               0100
 557         *      3.0     4       3       0101
 558         *      3.5     5               0110
 559         *      4.0             4       0111
 560         *      4.5                     1000
 561         *      5.0             5       1001
 562         */
 563#if defined(CONFIG_SYS_FSL_DDR1)
 564        caslat_ctrl = (cas_latency + 1) & 0x07;
 565#elif defined(CONFIG_SYS_FSL_DDR2)
 566        caslat_ctrl = 2 * cas_latency - 1;
 567#else
 568        /*
 569         * if the CAS latency more than 8 cycle,
 570         * we need set extend bit for it at
 571         * TIMING_CFG_3[EXT_CASLAT]
 572         */
 573        if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
 574                caslat_ctrl = 2 * cas_latency - 1;
 575        else
 576                caslat_ctrl = (cas_latency - 1) << 1;
 577#endif
 578
 579#ifdef CONFIG_SYS_FSL_DDR4
 580        refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
 581        wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 582        acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
 583        wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 584        if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 585                printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 586        else
 587                wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 588#else
 589        refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
 590        wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 591        acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
 592        wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 593        if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 594                printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 595        else
 596                wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 597#endif
 598        if (popts->otf_burst_chop_en)
 599                wrrec_mclk += 2;
 600
 601        /*
 602         * JEDEC has min requirement for tRRD
 603         */
 604#if defined(CONFIG_SYS_FSL_DDR3)
 605        if (acttoact_mclk < 4)
 606                acttoact_mclk = 4;
 607#endif
 608        /*
 609         * JEDEC has some min requirements for tWTR
 610         */
 611#if defined(CONFIG_SYS_FSL_DDR2)
 612        if (wrtord_mclk < 2)
 613                wrtord_mclk = 2;
 614#elif defined(CONFIG_SYS_FSL_DDR3)
 615        if (wrtord_mclk < 4)
 616                wrtord_mclk = 4;
 617#endif
 618        if (popts->otf_burst_chop_en)
 619                wrtord_mclk += 2;
 620
 621        ddr->timing_cfg_1 = (0
 622                | ((pretoact_mclk & 0x0F) << 28)
 623                | ((acttopre_mclk & 0x0F) << 24)
 624                | ((acttorw_mclk & 0xF) << 20)
 625                | ((caslat_ctrl & 0xF) << 16)
 626                | ((refrec_ctrl & 0xF) << 12)
 627                | ((wrrec_mclk & 0x0F) << 8)
 628                | ((acttoact_mclk & 0x0F) << 4)
 629                | ((wrtord_mclk & 0x0F) << 0)
 630                );
 631        debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 632}
 633
 634/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 635static void set_timing_cfg_2(const unsigned int ctrl_num,
 636                             fsl_ddr_cfg_regs_t *ddr,
 637                             const memctl_options_t *popts,
 638                             const common_timing_params_t *common_dimm,
 639                             unsigned int cas_latency,
 640                             unsigned int additive_latency)
 641{
 642        /* Additive latency */
 643        unsigned char add_lat_mclk;
 644        /* CAS-to-preamble override */
 645        unsigned short cpo;
 646        /* Write latency */
 647        unsigned char wr_lat;
 648        /*  Read to precharge (tRTP) */
 649        unsigned char rd_to_pre;
 650        /* Write command to write data strobe timing adjustment */
 651        unsigned char wr_data_delay;
 652        /* Minimum CKE pulse width (tCKE) */
 653        unsigned char cke_pls;
 654        /* Window for four activates (tFAW) */
 655        unsigned short four_act;
 656#ifdef CONFIG_SYS_FSL_DDR3
 657        const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 658#endif
 659
 660        /* FIXME add check that this must be less than acttorw_mclk */
 661        add_lat_mclk = additive_latency;
 662        cpo = popts->cpo_override;
 663
 664#if defined(CONFIG_SYS_FSL_DDR1)
 665        /*
 666         * This is a lie.  It should really be 1, but if it is
 667         * set to 1, bits overlap into the old controller's
 668         * otherwise unused ACSM field.  If we leave it 0, then
 669         * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 670         */
 671        wr_lat = 0;
 672#elif defined(CONFIG_SYS_FSL_DDR2)
 673        wr_lat = cas_latency - 1;
 674#else
 675        wr_lat = compute_cas_write_latency(ctrl_num);
 676#endif
 677
 678#ifdef CONFIG_SYS_FSL_DDR4
 679        rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 680#else
 681        rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 682#endif
 683        /*
 684         * JEDEC has some min requirements for tRTP
 685         */
 686#if defined(CONFIG_SYS_FSL_DDR2)
 687        if (rd_to_pre  < 2)
 688                rd_to_pre  = 2;
 689#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 690        if (rd_to_pre < 4)
 691                rd_to_pre = 4;
 692#endif
 693        if (popts->otf_burst_chop_en)
 694                rd_to_pre += 2; /* according to UM */
 695
 696        wr_data_delay = popts->write_data_delay;
 697#ifdef CONFIG_SYS_FSL_DDR4
 698        cpo = 0;
 699        cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 700#elif defined(CONFIG_SYS_FSL_DDR3)
 701        /*
 702         * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 703         *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 704         *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 705         */
 706        cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
 707                                        (mclk_ps > 1245 ? 5625 : 5000)));
 708#else
 709        cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 710#endif
 711        four_act = picos_to_mclk(ctrl_num,
 712                                 popts->tfaw_window_four_activates_ps);
 713
 714        ddr->timing_cfg_2 = (0
 715                | ((add_lat_mclk & 0xf) << 28)
 716                | ((cpo & 0x1f) << 23)
 717                | ((wr_lat & 0xf) << 19)
 718                | (((wr_lat & 0x10) >> 4) << 18)
 719                | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 720                | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 721                | ((cke_pls & 0x7) << 6)
 722                | ((four_act & 0x3f) << 0)
 723                );
 724        debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 725}
 726
 727/* DDR SDRAM Register Control Word */
 728static void set_ddr_sdram_rcw(const unsigned int ctrl_num,
 729                              fsl_ddr_cfg_regs_t *ddr,
 730                              const memctl_options_t *popts,
 731                              const common_timing_params_t *common_dimm)
 732{
 733        unsigned int ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 734        unsigned int rc0a, rc0f;
 735
 736        if (common_dimm->all_dimms_registered &&
 737            !common_dimm->all_dimms_unbuffered) {
 738                if (popts->rcw_override) {
 739                        ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 740                        ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 741                        ddr->ddr_sdram_rcw_3 = popts->rcw_3;
 742                } else {
 743                        rc0a = ddr_freq > 3200 ? 0x7 :
 744                               (ddr_freq > 2933 ? 0x6 :
 745                                (ddr_freq > 2666 ? 0x5 :
 746                                 (ddr_freq > 2400 ? 0x4 :
 747                                  (ddr_freq > 2133 ? 0x3 :
 748                                   (ddr_freq > 1866 ? 0x2 :
 749                                    (ddr_freq > 1600 ? 1 : 0))))));
 750                        rc0f = ddr_freq > 3200 ? 0x3 :
 751                               (ddr_freq > 2400 ? 0x2 :
 752                                (ddr_freq > 2133 ? 0x1 : 0));
 753                        ddr->ddr_sdram_rcw_1 =
 754                                common_dimm->rcw[0] << 28 | \
 755                                common_dimm->rcw[1] << 24 | \
 756                                common_dimm->rcw[2] << 20 | \
 757                                common_dimm->rcw[3] << 16 | \
 758                                common_dimm->rcw[4] << 12 | \
 759                                common_dimm->rcw[5] << 8 | \
 760                                common_dimm->rcw[6] << 4 | \
 761                                common_dimm->rcw[7];
 762                        ddr->ddr_sdram_rcw_2 =
 763                                common_dimm->rcw[8] << 28 | \
 764                                common_dimm->rcw[9] << 24 | \
 765                                rc0a << 20 | \
 766                                common_dimm->rcw[11] << 16 | \
 767                                common_dimm->rcw[12] << 12 | \
 768                                common_dimm->rcw[13] << 8 | \
 769                                common_dimm->rcw[14] << 4 | \
 770                                rc0f;
 771                        ddr->ddr_sdram_rcw_3 =
 772                                ((ddr_freq - 1260 + 19) / 20) << 8;
 773                }
 774                debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n",
 775                      ddr->ddr_sdram_rcw_1);
 776                debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n",
 777                      ddr->ddr_sdram_rcw_2);
 778                debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n",
 779                      ddr->ddr_sdram_rcw_3);
 780        }
 781}
 782
 783/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 784static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 785                               const memctl_options_t *popts,
 786                               const common_timing_params_t *common_dimm)
 787{
 788        unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 789        unsigned int sren;              /* Self refresh enable (during sleep) */
 790        unsigned int ecc_en;            /* ECC enable. */
 791        unsigned int rd_en;             /* Registered DIMM enable */
 792        unsigned int sdram_type;        /* Type of SDRAM */
 793        unsigned int dyn_pwr;           /* Dynamic power management mode */
 794        unsigned int dbw;               /* DRAM dta bus width */
 795        unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 796        unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 797        unsigned int threet_en;         /* Enable 3T timing */
 798        unsigned int twot_en;           /* Enable 2T timing */
 799        unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 800        unsigned int x32_en = 0;        /* x32 enable */
 801        unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 802        unsigned int hse;               /* Global half strength override */
 803        unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 804        unsigned int mem_halt = 0;      /* memory controller halt */
 805        unsigned int bi = 0;            /* Bypass initialization */
 806
 807        mem_en = 1;
 808        sren = popts->self_refresh_in_sleep;
 809        if (common_dimm->all_dimms_ecc_capable) {
 810                /* Allow setting of ECC only if all DIMMs are ECC. */
 811                ecc_en = popts->ecc_mode;
 812        } else {
 813                ecc_en = 0;
 814        }
 815
 816        if (common_dimm->all_dimms_registered &&
 817            !common_dimm->all_dimms_unbuffered) {
 818                rd_en = 1;
 819                twot_en = 0;
 820        } else {
 821                rd_en = 0;
 822                twot_en = popts->twot_en;
 823        }
 824
 825        sdram_type = CONFIG_FSL_SDRAM_TYPE;
 826
 827        dyn_pwr = popts->dynamic_power;
 828        dbw = popts->data_bus_width;
 829        /* 8-beat burst enable DDR-III case
 830         * we must clear it when use the on-the-fly mode,
 831         * must set it when use the 32-bits bus mode.
 832         */
 833        if ((sdram_type == SDRAM_TYPE_DDR3) ||
 834            (sdram_type == SDRAM_TYPE_DDR4)) {
 835                if (popts->burst_length == DDR_BL8)
 836                        eight_be = 1;
 837                if (popts->burst_length == DDR_OTF)
 838                        eight_be = 0;
 839                if (dbw == 0x1)
 840                        eight_be = 1;
 841        }
 842
 843        threet_en = popts->threet_en;
 844        ba_intlv_ctl = popts->ba_intlv_ctl;
 845        hse = popts->half_strength_driver_enable;
 846
 847        /* set when ddr bus width < 64 */
 848        acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 849
 850        ddr->ddr_sdram_cfg = (0
 851                        | ((mem_en & 0x1) << 31)
 852                        | ((sren & 0x1) << 30)
 853                        | ((ecc_en & 0x1) << 29)
 854                        | ((rd_en & 0x1) << 28)
 855                        | ((sdram_type & 0x7) << 24)
 856                        | ((dyn_pwr & 0x1) << 21)
 857                        | ((dbw & 0x3) << 19)
 858                        | ((eight_be & 0x1) << 18)
 859                        | ((ncap & 0x1) << 17)
 860                        | ((threet_en & 0x1) << 16)
 861                        | ((twot_en & 0x1) << 15)
 862                        | ((ba_intlv_ctl & 0x7F) << 8)
 863                        | ((x32_en & 0x1) << 5)
 864                        | ((pchb8 & 0x1) << 4)
 865                        | ((hse & 0x1) << 3)
 866                        | ((acc_ecc_en & 0x1) << 2)
 867                        | ((mem_halt & 0x1) << 1)
 868                        | ((bi & 0x1) << 0)
 869                        );
 870        debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 871}
 872
 873/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 874static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 875                               fsl_ddr_cfg_regs_t *ddr,
 876                               const memctl_options_t *popts,
 877                               const unsigned int unq_mrs_en)
 878{
 879        unsigned int frc_sr = 0;        /* Force self refresh */
 880        unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 881        unsigned int odt_cfg = 0;       /* ODT configuration */
 882        unsigned int num_pr;            /* Number of posted refreshes */
 883        unsigned int slow = 0;          /* DDR will be run less than 1250 */
 884        unsigned int x4_en = 0;         /* x4 DRAM enable */
 885        unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 886        unsigned int ap_en;             /* Address Parity Enable */
 887        unsigned int d_init;            /* DRAM data initialization */
 888        unsigned int rcw_en = 0;        /* Register Control Word Enable */
 889        unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 890        unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 891        int i;
 892#ifndef CONFIG_SYS_FSL_DDR4
 893        unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 894        unsigned int dqs_cfg;           /* DQS configuration */
 895
 896        dqs_cfg = popts->dqs_config;
 897#endif
 898        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 899                if (popts->cs_local_opts[i].odt_rd_cfg
 900                        || popts->cs_local_opts[i].odt_wr_cfg) {
 901                        odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 902                        break;
 903                }
 904        }
 905        sr_ie = popts->self_refresh_interrupt_en;
 906        num_pr = popts->package_3ds + 1;
 907
 908        /*
 909         * 8572 manual says
 910         *     {TIMING_CFG_1[PRETOACT]
 911         *      + [DDR_SDRAM_CFG_2[NUM_PR]
 912         *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 913         *      << DDR_SDRAM_INTERVAL[REFINT]
 914         */
 915#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 916        obc_cfg = popts->otf_burst_chop_en;
 917#else
 918        obc_cfg = 0;
 919#endif
 920
 921#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 922        slow = get_ddr_freq(ctrl_num) < 1249000000;
 923#endif
 924
 925        if (popts->registered_dimm_en)
 926                rcw_en = 1;
 927
 928        /* DDR4 can have address parity for UDIMM and discrete */
 929        if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
 930            (!popts->registered_dimm_en)) {
 931                ap_en = 0;
 932        } else {
 933                ap_en = popts->ap_en;
 934        }
 935
 936        x4_en = popts->x4_en ? 1 : 0;
 937
 938#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 939        /* Use the DDR controller to auto initialize memory. */
 940        d_init = popts->ecc_init_using_memctl;
 941        ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 942        debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 943#else
 944        /* Memory will be initialized via DMA, or not at all. */
 945        d_init = 0;
 946#endif
 947
 948#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 949        md_en = popts->mirrored_dimm;
 950#endif
 951        qd_en = popts->quad_rank_present ? 1 : 0;
 952        ddr->ddr_sdram_cfg_2 = (0
 953                | ((frc_sr & 0x1) << 31)
 954                | ((sr_ie & 0x1) << 30)
 955#ifndef CONFIG_SYS_FSL_DDR4
 956                | ((dll_rst_dis & 0x1) << 29)
 957                | ((dqs_cfg & 0x3) << 26)
 958#endif
 959                | ((odt_cfg & 0x3) << 21)
 960                | ((num_pr & 0xf) << 12)
 961                | ((slow & 1) << 11)
 962                | (x4_en << 10)
 963                | (qd_en << 9)
 964                | (unq_mrs_en << 8)
 965                | ((obc_cfg & 0x1) << 6)
 966                | ((ap_en & 0x1) << 5)
 967                | ((d_init & 0x1) << 4)
 968                | ((rcw_en & 0x1) << 2)
 969                | ((md_en & 0x1) << 0)
 970                );
 971        debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 972}
 973
 974#ifdef CONFIG_SYS_FSL_DDR4
 975/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 976static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
 977                                fsl_ddr_cfg_regs_t *ddr,
 978                                const memctl_options_t *popts,
 979                                const common_timing_params_t *common_dimm,
 980                                const unsigned int unq_mrs_en)
 981{
 982        unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 983        unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 984        int i;
 985        unsigned int wr_crc = 0;        /* Disable */
 986        unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 987        unsigned int srt = 0;   /* self-refresh temerature, normal range */
 988        unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 989        unsigned int mpr = 0;   /* serial */
 990        unsigned int wc_lat;
 991        const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 992
 993        if (popts->rtt_override)
 994                rtt_wr = popts->rtt_wr_override_value;
 995        else
 996                rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 997
 998        if (common_dimm->extended_op_srt)
 999                srt = common_dimm->extended_op_srt;
1000
1001        esdmode2 = (0
1002                | ((wr_crc & 0x1) << 12)
1003                | ((rtt_wr & 0x3) << 9)
1004                | ((srt & 0x3) << 6)
1005                | ((cwl & 0x7) << 3));
1006
1007        if (mclk_ps >= 1250)
1008                wc_lat = 0;
1009        else if (mclk_ps >= 833)
1010                wc_lat = 1;
1011        else
1012                wc_lat = 2;
1013
1014        esdmode3 = (0
1015                | ((mpr & 0x3) << 11)
1016                | ((wc_lat & 0x3) << 9));
1017
1018        ddr->ddr_sdram_mode_2 = (0
1019                                 | ((esdmode2 & 0xFFFF) << 16)
1020                                 | ((esdmode3 & 0xFFFF) << 0)
1021                                 );
1022        debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1023
1024        if (unq_mrs_en) {       /* unique mode registers are supported */
1025                for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1026                        if (popts->rtt_override)
1027                                rtt_wr = popts->rtt_wr_override_value;
1028                        else
1029                                rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1030
1031                        esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1032                        esdmode2 |= (rtt_wr & 0x3) << 9;
1033                        switch (i) {
1034                        case 1:
1035                                ddr->ddr_sdram_mode_4 = (0
1036                                        | ((esdmode2 & 0xFFFF) << 16)
1037                                        | ((esdmode3 & 0xFFFF) << 0)
1038                                        );
1039                                break;
1040                        case 2:
1041                                ddr->ddr_sdram_mode_6 = (0
1042                                        | ((esdmode2 & 0xFFFF) << 16)
1043                                        | ((esdmode3 & 0xFFFF) << 0)
1044                                        );
1045                                break;
1046                        case 3:
1047                                ddr->ddr_sdram_mode_8 = (0
1048                                        | ((esdmode2 & 0xFFFF) << 16)
1049                                        | ((esdmode3 & 0xFFFF) << 0)
1050                                        );
1051                                break;
1052                        }
1053                }
1054                debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1055                      ddr->ddr_sdram_mode_4);
1056                debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1057                      ddr->ddr_sdram_mode_6);
1058                debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1059                      ddr->ddr_sdram_mode_8);
1060        }
1061}
1062#elif defined(CONFIG_SYS_FSL_DDR3)
1063/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1064static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1065                                fsl_ddr_cfg_regs_t *ddr,
1066                                const memctl_options_t *popts,
1067                                const common_timing_params_t *common_dimm,
1068                                const unsigned int unq_mrs_en)
1069{
1070        unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1071        unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1072        int i;
1073        unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
1074        unsigned int srt = 0;   /* self-refresh temerature, normal range */
1075        unsigned int asr = 0;   /* auto self-refresh disable */
1076        unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1077        unsigned int pasr = 0;  /* partial array self refresh disable */
1078
1079        if (popts->rtt_override)
1080                rtt_wr = popts->rtt_wr_override_value;
1081        else
1082                rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1083
1084        if (common_dimm->extended_op_srt)
1085                srt = common_dimm->extended_op_srt;
1086
1087        esdmode2 = (0
1088                | ((rtt_wr & 0x3) << 9)
1089                | ((srt & 0x1) << 7)
1090                | ((asr & 0x1) << 6)
1091                | ((cwl & 0x7) << 3)
1092                | ((pasr & 0x7) << 0));
1093        ddr->ddr_sdram_mode_2 = (0
1094                                 | ((esdmode2 & 0xFFFF) << 16)
1095                                 | ((esdmode3 & 0xFFFF) << 0)
1096                                 );
1097        debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1098
1099        if (unq_mrs_en) {       /* unique mode registers are supported */
1100                for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1101                        if (popts->rtt_override)
1102                                rtt_wr = popts->rtt_wr_override_value;
1103                        else
1104                                rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1105
1106                        esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1107                        esdmode2 |= (rtt_wr & 0x3) << 9;
1108                        switch (i) {
1109                        case 1:
1110                                ddr->ddr_sdram_mode_4 = (0
1111                                        | ((esdmode2 & 0xFFFF) << 16)
1112                                        | ((esdmode3 & 0xFFFF) << 0)
1113                                        );
1114                                break;
1115                        case 2:
1116                                ddr->ddr_sdram_mode_6 = (0
1117                                        | ((esdmode2 & 0xFFFF) << 16)
1118                                        | ((esdmode3 & 0xFFFF) << 0)
1119                                        );
1120                                break;
1121                        case 3:
1122                                ddr->ddr_sdram_mode_8 = (0
1123                                        | ((esdmode2 & 0xFFFF) << 16)
1124                                        | ((esdmode3 & 0xFFFF) << 0)
1125                                        );
1126                                break;
1127                        }
1128                }
1129                debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1130                        ddr->ddr_sdram_mode_4);
1131                debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1132                        ddr->ddr_sdram_mode_6);
1133                debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1134                        ddr->ddr_sdram_mode_8);
1135        }
1136}
1137
1138#else /* for DDR2 and DDR1 */
1139/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1140static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1141                                fsl_ddr_cfg_regs_t *ddr,
1142                                const memctl_options_t *popts,
1143                                const common_timing_params_t *common_dimm,
1144                                const unsigned int unq_mrs_en)
1145{
1146        unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1147        unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1148
1149        ddr->ddr_sdram_mode_2 = (0
1150                                 | ((esdmode2 & 0xFFFF) << 16)
1151                                 | ((esdmode3 & 0xFFFF) << 0)
1152                                 );
1153        debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1154}
1155#endif
1156
1157#ifdef CONFIG_SYS_FSL_DDR4
1158/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1159static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1160                                const memctl_options_t *popts,
1161                                const common_timing_params_t *common_dimm,
1162                                const unsigned int unq_mrs_en)
1163{
1164        int i;
1165        unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1166        unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1167        int rtt_park = 0;
1168        bool four_cs = false;
1169        const unsigned int mclk_ps = get_memory_clk_period_ps(0);
1170
1171#if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1172        if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1173            (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1174            (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1175            (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1176                four_cs = true;
1177#endif
1178        if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1179                esdmode5 = 0x00000500;  /* Data mask enable, RTT_PARK CS0 */
1180                rtt_park = four_cs ? 0 : 1;
1181        } else {
1182                esdmode5 = 0x00000400;  /* Data mask enabled */
1183        }
1184
1185        /*
1186         * For DDR3, set C/A latency if address parity is enabled.
1187         * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is
1188         * handled by register chip and RCW settings.
1189         */
1190        if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1191            ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1192             !popts->registered_dimm_en)) {
1193                if (mclk_ps >= 935) {
1194                        /* for DDR4-1600/1866/2133 */
1195                        esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1196                } else if (mclk_ps >= 833) {
1197                        /* for DDR4-2400 */
1198                        esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1199                } else {
1200                        printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1201                }
1202        }
1203
1204        ddr->ddr_sdram_mode_9 = (0
1205                                 | ((esdmode4 & 0xffff) << 16)
1206                                 | ((esdmode5 & 0xffff) << 0)
1207                                );
1208
1209        /* Normally only the first enabled CS use 0x500, others use 0x400
1210         * But when four chip-selects are all enabled, all mode registers
1211         * need 0x500 to park.
1212         */
1213
1214        debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9);
1215        if (unq_mrs_en) {       /* unique mode registers are supported */
1216                for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1217                        if (!rtt_park &&
1218                            (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1219                                esdmode5 |= 0x00000500; /* RTT_PARK */
1220                                rtt_park = four_cs ? 0 : 1;
1221                        } else {
1222                                esdmode5 = 0x00000400;
1223                        }
1224
1225                        if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1226                            ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1227                             !popts->registered_dimm_en)) {
1228                                if (mclk_ps >= 935) {
1229                                        /* for DDR4-1600/1866/2133 */
1230                                        esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1231                                } else if (mclk_ps >= 833) {
1232                                        /* for DDR4-2400 */
1233                                        esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1234                                } else {
1235                                        printf("parity: mclk_ps = %d not supported\n",
1236                                               mclk_ps);
1237                                }
1238                        }
1239
1240                        switch (i) {
1241                        case 1:
1242                                ddr->ddr_sdram_mode_11 = (0
1243                                        | ((esdmode4 & 0xFFFF) << 16)
1244                                        | ((esdmode5 & 0xFFFF) << 0)
1245                                        );
1246                                break;
1247                        case 2:
1248                                ddr->ddr_sdram_mode_13 = (0
1249                                        | ((esdmode4 & 0xFFFF) << 16)
1250                                        | ((esdmode5 & 0xFFFF) << 0)
1251                                        );
1252                                break;
1253                        case 3:
1254                                ddr->ddr_sdram_mode_15 = (0
1255                                        | ((esdmode4 & 0xFFFF) << 16)
1256                                        | ((esdmode5 & 0xFFFF) << 0)
1257                                        );
1258                                break;
1259                        }
1260                }
1261                debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1262                      ddr->ddr_sdram_mode_11);
1263                debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1264                      ddr->ddr_sdram_mode_13);
1265                debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1266                      ddr->ddr_sdram_mode_15);
1267        }
1268}
1269
1270/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1271static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1272                                fsl_ddr_cfg_regs_t *ddr,
1273                                const memctl_options_t *popts,
1274                                const common_timing_params_t *common_dimm,
1275                                const unsigned int unq_mrs_en)
1276{
1277        int i;
1278        unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1279        unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1280        unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1281
1282        esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1283
1284        if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1285                esdmode6 |= 1 << 6;     /* Range 2 */
1286
1287        ddr->ddr_sdram_mode_10 = (0
1288                                 | ((esdmode6 & 0xffff) << 16)
1289                                 | ((esdmode7 & 0xffff) << 0)
1290                                );
1291        debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10);
1292        if (unq_mrs_en) {       /* unique mode registers are supported */
1293                for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1294                        switch (i) {
1295                        case 1:
1296                                ddr->ddr_sdram_mode_12 = (0
1297                                        | ((esdmode6 & 0xFFFF) << 16)
1298                                        | ((esdmode7 & 0xFFFF) << 0)
1299                                        );
1300                                break;
1301                        case 2:
1302                                ddr->ddr_sdram_mode_14 = (0
1303                                        | ((esdmode6 & 0xFFFF) << 16)
1304                                        | ((esdmode7 & 0xFFFF) << 0)
1305                                        );
1306                                break;
1307                        case 3:
1308                                ddr->ddr_sdram_mode_16 = (0
1309                                        | ((esdmode6 & 0xFFFF) << 16)
1310                                        | ((esdmode7 & 0xFFFF) << 0)
1311                                        );
1312                                break;
1313                        }
1314                }
1315                debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1316                      ddr->ddr_sdram_mode_12);
1317                debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1318                      ddr->ddr_sdram_mode_14);
1319                debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1320                      ddr->ddr_sdram_mode_16);
1321        }
1322}
1323
1324#endif
1325
1326/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1327static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1328                                fsl_ddr_cfg_regs_t *ddr,
1329                                const memctl_options_t *popts,
1330                                const common_timing_params_t *common_dimm)
1331{
1332        unsigned int refint;    /* Refresh interval */
1333        unsigned int bstopre;   /* Precharge interval */
1334
1335        refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1336
1337        bstopre = popts->bstopre;
1338
1339        /* refint field used 0x3FFF in earlier controllers */
1340        ddr->ddr_sdram_interval = (0
1341                                   | ((refint & 0xFFFF) << 16)
1342                                   | ((bstopre & 0x3FFF) << 0)
1343                                   );
1344        debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1345}
1346
1347#ifdef CONFIG_SYS_FSL_DDR4
1348/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1349static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1350                               fsl_ddr_cfg_regs_t *ddr,
1351                               const memctl_options_t *popts,
1352                               const common_timing_params_t *common_dimm,
1353                               unsigned int cas_latency,
1354                               unsigned int additive_latency,
1355                               const unsigned int unq_mrs_en)
1356{
1357        int i;
1358        unsigned short esdmode;         /* Extended SDRAM mode */
1359        unsigned short sdmode;          /* SDRAM mode */
1360
1361        /* Mode Register - MR1 */
1362        unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1363        unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1364        unsigned int rtt;
1365        unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1366        unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1367        unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1368        unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1369                                                       0=Disable (Test/Debug) */
1370
1371        /* Mode Register - MR0 */
1372        unsigned int wr = 0;    /* Write Recovery */
1373        unsigned int dll_rst;   /* DLL Reset */
1374        unsigned int mode;      /* Normal=0 or Test=1 */
1375        unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1376        /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1377        unsigned int bt;
1378        unsigned int bl;        /* BL: Burst Length */
1379
1380        unsigned int wr_mclk;
1381        /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1382        static const u8 wr_table[] = {
1383                0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1384        /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1385        static const u8 cas_latency_table[] = {
1386                0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1387                9, 9, 10, 10, 11, 11};
1388
1389        if (popts->rtt_override)
1390                rtt = popts->rtt_override_value;
1391        else
1392                rtt = popts->cs_local_opts[0].odt_rtt_norm;
1393
1394        if (additive_latency == (cas_latency - 1))
1395                al = 1;
1396        if (additive_latency == (cas_latency - 2))
1397                al = 2;
1398
1399        if (popts->quad_rank_present)
1400                dic = 1;        /* output driver impedance 240/7 ohm */
1401
1402        /*
1403         * The esdmode value will also be used for writing
1404         * MR1 during write leveling for DDR3, although the
1405         * bits specifically related to the write leveling
1406         * scheme will be handled automatically by the DDR
1407         * controller. so we set the wrlvl_en = 0 here.
1408         */
1409        esdmode = (0
1410                | ((qoff & 0x1) << 12)
1411                | ((tdqs_en & 0x1) << 11)
1412                | ((rtt & 0x7) << 8)
1413                | ((wrlvl_en & 0x1) << 7)
1414                | ((al & 0x3) << 3)
1415                | ((dic & 0x3) << 1)   /* DIC field is split */
1416                | ((dll_en & 0x1) << 0)
1417                );
1418
1419        /*
1420         * DLL control for precharge PD
1421         * 0=slow exit DLL off (tXPDLL)
1422         * 1=fast exit DLL on (tXP)
1423         */
1424
1425        wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1426        if (wr_mclk <= 24) {
1427                wr = wr_table[wr_mclk - 10];
1428        } else {
1429                printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1430                       wr_mclk);
1431        }
1432
1433        dll_rst = 0;    /* dll no reset */
1434        mode = 0;       /* normal mode */
1435
1436        /* look up table to get the cas latency bits */
1437        if (cas_latency >= 9 && cas_latency <= 24)
1438                caslat = cas_latency_table[cas_latency - 9];
1439        else
1440                printf("Error: unsupported cas latency for mode register\n");
1441
1442        bt = 0; /* Nibble sequential */
1443
1444        switch (popts->burst_length) {
1445        case DDR_BL8:
1446                bl = 0;
1447                break;
1448        case DDR_OTF:
1449                bl = 1;
1450                break;
1451        case DDR_BC4:
1452                bl = 2;
1453                break;
1454        default:
1455                printf("Error: invalid burst length of %u specified. ",
1456                       popts->burst_length);
1457                puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1458                bl = 1;
1459                break;
1460        }
1461
1462        sdmode = (0
1463                  | ((wr & 0x7) << 9)
1464                  | ((dll_rst & 0x1) << 8)
1465                  | ((mode & 0x1) << 7)
1466                  | (((caslat >> 1) & 0x7) << 4)
1467                  | ((bt & 0x1) << 3)
1468                  | ((caslat & 1) << 2)
1469                  | ((bl & 0x3) << 0)
1470                  );
1471
1472        ddr->ddr_sdram_mode = (0
1473                               | ((esdmode & 0xFFFF) << 16)
1474                               | ((sdmode & 0xFFFF) << 0)
1475                               );
1476
1477        debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1478
1479        if (unq_mrs_en) {       /* unique mode registers are supported */
1480                for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1481                        if (popts->rtt_override)
1482                                rtt = popts->rtt_override_value;
1483                        else
1484                                rtt = popts->cs_local_opts[i].odt_rtt_norm;
1485
1486                        esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1487                        esdmode |= (rtt & 0x7) << 8;
1488                        switch (i) {
1489                        case 1:
1490                                ddr->ddr_sdram_mode_3 = (0
1491                                       | ((esdmode & 0xFFFF) << 16)
1492                                       | ((sdmode & 0xFFFF) << 0)
1493                                       );
1494                                break;
1495                        case 2:
1496                                ddr->ddr_sdram_mode_5 = (0
1497                                       | ((esdmode & 0xFFFF) << 16)
1498                                       | ((sdmode & 0xFFFF) << 0)
1499                                       );
1500                                break;
1501                        case 3:
1502                                ddr->ddr_sdram_mode_7 = (0
1503                                       | ((esdmode & 0xFFFF) << 16)
1504                                       | ((sdmode & 0xFFFF) << 0)
1505                                       );
1506                                break;
1507                        }
1508                }
1509                debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1510                      ddr->ddr_sdram_mode_3);
1511                debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1512                      ddr->ddr_sdram_mode_5);
1513                debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1514                      ddr->ddr_sdram_mode_5);
1515        }
1516}
1517
1518#elif defined(CONFIG_SYS_FSL_DDR3)
1519/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1520static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1521                               fsl_ddr_cfg_regs_t *ddr,
1522                               const memctl_options_t *popts,
1523                               const common_timing_params_t *common_dimm,
1524                               unsigned int cas_latency,
1525                               unsigned int additive_latency,
1526                               const unsigned int unq_mrs_en)
1527{
1528        int i;
1529        unsigned short esdmode;         /* Extended SDRAM mode */
1530        unsigned short sdmode;          /* SDRAM mode */
1531
1532        /* Mode Register - MR1 */
1533        unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1534        unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1535        unsigned int rtt;
1536        unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1537        unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1538        unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1539        unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1540                                                       1=Disable (Test/Debug) */
1541
1542        /* Mode Register - MR0 */
1543        unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1544        unsigned int wr = 0;    /* Write Recovery */
1545        unsigned int dll_rst;   /* DLL Reset */
1546        unsigned int mode;      /* Normal=0 or Test=1 */
1547        unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1548        /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1549        unsigned int bt;
1550        unsigned int bl;        /* BL: Burst Length */
1551
1552        unsigned int wr_mclk;
1553        /*
1554         * DDR_SDRAM_MODE doesn't support 9,11,13,15
1555         * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1556         * for this table
1557         */
1558        static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1559
1560        if (popts->rtt_override)
1561                rtt = popts->rtt_override_value;
1562        else
1563                rtt = popts->cs_local_opts[0].odt_rtt_norm;
1564
1565        if (additive_latency == (cas_latency - 1))
1566                al = 1;
1567        if (additive_latency == (cas_latency - 2))
1568                al = 2;
1569
1570        if (popts->quad_rank_present)
1571                dic = 1;        /* output driver impedance 240/7 ohm */
1572
1573        /*
1574         * The esdmode value will also be used for writing
1575         * MR1 during write leveling for DDR3, although the
1576         * bits specifically related to the write leveling
1577         * scheme will be handled automatically by the DDR
1578         * controller. so we set the wrlvl_en = 0 here.
1579         */
1580        esdmode = (0
1581                | ((qoff & 0x1) << 12)
1582                | ((tdqs_en & 0x1) << 11)
1583                | ((rtt & 0x4) << 7)   /* rtt field is split */
1584                | ((wrlvl_en & 0x1) << 7)
1585                | ((rtt & 0x2) << 5)   /* rtt field is split */
1586                | ((dic & 0x2) << 4)   /* DIC field is split */
1587                | ((al & 0x3) << 3)
1588                | ((rtt & 0x1) << 2)  /* rtt field is split */
1589                | ((dic & 0x1) << 1)   /* DIC field is split */
1590                | ((dll_en & 0x1) << 0)
1591                );
1592
1593        /*
1594         * DLL control for precharge PD
1595         * 0=slow exit DLL off (tXPDLL)
1596         * 1=fast exit DLL on (tXP)
1597         */
1598        dll_on = 1;
1599
1600        wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1601        if (wr_mclk <= 16) {
1602                wr = wr_table[wr_mclk - 5];
1603        } else {
1604                printf("Error: unsupported write recovery for mode register "
1605                       "wr_mclk = %d\n", wr_mclk);
1606        }
1607
1608        dll_rst = 0;    /* dll no reset */
1609        mode = 0;       /* normal mode */
1610
1611        /* look up table to get the cas latency bits */
1612        if (cas_latency >= 5 && cas_latency <= 16) {
1613                unsigned char cas_latency_table[] = {
1614                        0x2,    /* 5 clocks */
1615                        0x4,    /* 6 clocks */
1616                        0x6,    /* 7 clocks */
1617                        0x8,    /* 8 clocks */
1618                        0xa,    /* 9 clocks */
1619                        0xc,    /* 10 clocks */
1620                        0xe,    /* 11 clocks */
1621                        0x1,    /* 12 clocks */
1622                        0x3,    /* 13 clocks */
1623                        0x5,    /* 14 clocks */
1624                        0x7,    /* 15 clocks */
1625                        0x9,    /* 16 clocks */
1626                };
1627                caslat = cas_latency_table[cas_latency - 5];
1628        } else {
1629                printf("Error: unsupported cas latency for mode register\n");
1630        }
1631
1632        bt = 0; /* Nibble sequential */
1633
1634        switch (popts->burst_length) {
1635        case DDR_BL8:
1636                bl = 0;
1637                break;
1638        case DDR_OTF:
1639                bl = 1;
1640                break;
1641        case DDR_BC4:
1642                bl = 2;
1643                break;
1644        default:
1645                printf("Error: invalid burst length of %u specified. "
1646                        " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1647                        popts->burst_length);
1648                bl = 1;
1649                break;
1650        }
1651
1652        sdmode = (0
1653                  | ((dll_on & 0x1) << 12)
1654                  | ((wr & 0x7) << 9)
1655                  | ((dll_rst & 0x1) << 8)
1656                  | ((mode & 0x1) << 7)
1657                  | (((caslat >> 1) & 0x7) << 4)
1658                  | ((bt & 0x1) << 3)
1659                  | ((caslat & 1) << 2)
1660                  | ((bl & 0x3) << 0)
1661                  );
1662
1663        ddr->ddr_sdram_mode = (0
1664                               | ((esdmode & 0xFFFF) << 16)
1665                               | ((sdmode & 0xFFFF) << 0)
1666                               );
1667
1668        debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1669
1670        if (unq_mrs_en) {       /* unique mode registers are supported */
1671                for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1672                        if (popts->rtt_override)
1673                                rtt = popts->rtt_override_value;
1674                        else
1675                                rtt = popts->cs_local_opts[i].odt_rtt_norm;
1676
1677                        esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1678                        esdmode |= (0
1679                                | ((rtt & 0x4) << 7)   /* rtt field is split */
1680                                | ((rtt & 0x2) << 5)   /* rtt field is split */
1681                                | ((rtt & 0x1) << 2)  /* rtt field is split */
1682                                );
1683                        switch (i) {
1684                        case 1:
1685                                ddr->ddr_sdram_mode_3 = (0
1686                                       | ((esdmode & 0xFFFF) << 16)
1687                                       | ((sdmode & 0xFFFF) << 0)
1688                                       );
1689                                break;
1690                        case 2:
1691                                ddr->ddr_sdram_mode_5 = (0
1692                                       | ((esdmode & 0xFFFF) << 16)
1693                                       | ((sdmode & 0xFFFF) << 0)
1694                                       );
1695                                break;
1696                        case 3:
1697                                ddr->ddr_sdram_mode_7 = (0
1698                                       | ((esdmode & 0xFFFF) << 16)
1699                                       | ((sdmode & 0xFFFF) << 0)
1700                                       );
1701                                break;
1702                        }
1703                }
1704                debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1705                        ddr->ddr_sdram_mode_3);
1706                debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1707                        ddr->ddr_sdram_mode_5);
1708                debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1709                        ddr->ddr_sdram_mode_5);
1710        }
1711}
1712
1713#else /* !CONFIG_SYS_FSL_DDR3 */
1714
1715/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1716static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1717                               fsl_ddr_cfg_regs_t *ddr,
1718                               const memctl_options_t *popts,
1719                               const common_timing_params_t *common_dimm,
1720                               unsigned int cas_latency,
1721                               unsigned int additive_latency,
1722                               const unsigned int unq_mrs_en)
1723{
1724        unsigned short esdmode;         /* Extended SDRAM mode */
1725        unsigned short sdmode;          /* SDRAM mode */
1726
1727        /*
1728         * FIXME: This ought to be pre-calculated in a
1729         * technology-specific routine,
1730         * e.g. compute_DDR2_mode_register(), and then the
1731         * sdmode and esdmode passed in as part of common_dimm.
1732         */
1733
1734        /* Extended Mode Register */
1735        unsigned int mrs = 0;           /* Mode Register Set */
1736        unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1737        unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1738        unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1739        unsigned int ocd = 0;           /* 0x0=OCD not supported,
1740                                           0x7=OCD default state */
1741        unsigned int rtt;
1742        unsigned int al;                /* Posted CAS# additive latency (AL) */
1743        unsigned int ods = 0;           /* Output Drive Strength:
1744                                                0 = Full strength (18ohm)
1745                                                1 = Reduced strength (4ohm) */
1746        unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1747                                                       1=Disable (Test/Debug) */
1748
1749        /* Mode Register (MR) */
1750        unsigned int mr;        /* Mode Register Definition */
1751        unsigned int pd;        /* Power-Down Mode */
1752        unsigned int wr;        /* Write Recovery */
1753        unsigned int dll_res;   /* DLL Reset */
1754        unsigned int mode;      /* Normal=0 or Test=1 */
1755        unsigned int caslat = 0;/* CAS# latency */
1756        /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1757        unsigned int bt;
1758        unsigned int bl;        /* BL: Burst Length */
1759
1760        dqs_en = !popts->dqs_config;
1761        rtt = fsl_ddr_get_rtt();
1762
1763        al = additive_latency;
1764
1765        esdmode = (0
1766                | ((mrs & 0x3) << 14)
1767                | ((outputs & 0x1) << 12)
1768                | ((rdqs_en & 0x1) << 11)
1769                | ((dqs_en & 0x1) << 10)
1770                | ((ocd & 0x7) << 7)
1771                | ((rtt & 0x2) << 5)   /* rtt field is split */
1772                | ((al & 0x7) << 3)
1773                | ((rtt & 0x1) << 2)   /* rtt field is split */
1774                | ((ods & 0x1) << 1)
1775                | ((dll_en & 0x1) << 0)
1776                );
1777
1778        mr = 0;          /* FIXME: CHECKME */
1779
1780        /*
1781         * 0 = Fast Exit (Normal)
1782         * 1 = Slow Exit (Low Power)
1783         */
1784        pd = 0;
1785
1786#if defined(CONFIG_SYS_FSL_DDR1)
1787        wr = 0;       /* Historical */
1788#elif defined(CONFIG_SYS_FSL_DDR2)
1789        wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1790#endif
1791        dll_res = 0;
1792        mode = 0;
1793
1794#if defined(CONFIG_SYS_FSL_DDR1)
1795        if (1 <= cas_latency && cas_latency <= 4) {
1796                unsigned char mode_caslat_table[4] = {
1797                        0x5,    /* 1.5 clocks */
1798                        0x2,    /* 2.0 clocks */
1799                        0x6,    /* 2.5 clocks */
1800                        0x3     /* 3.0 clocks */
1801                };
1802                caslat = mode_caslat_table[cas_latency - 1];
1803        } else {
1804                printf("Warning: unknown cas_latency %d\n", cas_latency);
1805        }
1806#elif defined(CONFIG_SYS_FSL_DDR2)
1807        caslat = cas_latency;
1808#endif
1809        bt = 0;
1810
1811        switch (popts->burst_length) {
1812        case DDR_BL4:
1813                bl = 2;
1814                break;
1815        case DDR_BL8:
1816                bl = 3;
1817                break;
1818        default:
1819                printf("Error: invalid burst length of %u specified. "
1820                        " Defaulting to 4 beats.\n",
1821                        popts->burst_length);
1822                bl = 2;
1823                break;
1824        }
1825
1826        sdmode = (0
1827                  | ((mr & 0x3) << 14)
1828                  | ((pd & 0x1) << 12)
1829                  | ((wr & 0x7) << 9)
1830                  | ((dll_res & 0x1) << 8)
1831                  | ((mode & 0x1) << 7)
1832                  | ((caslat & 0x7) << 4)
1833                  | ((bt & 0x1) << 3)
1834                  | ((bl & 0x7) << 0)
1835                  );
1836
1837        ddr->ddr_sdram_mode = (0
1838                               | ((esdmode & 0xFFFF) << 16)
1839                               | ((sdmode & 0xFFFF) << 0)
1840                               );
1841        debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1842}
1843#endif
1844
1845/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1846static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1847{
1848        unsigned int init_value;        /* Initialization value */
1849
1850#ifdef CONFIG_MEM_INIT_VALUE
1851        init_value = CONFIG_MEM_INIT_VALUE;
1852#else
1853        init_value = 0xDEADBEEF;
1854#endif
1855        ddr->ddr_data_init = init_value;
1856}
1857
1858/*
1859 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1860 * The old controller on the 8540/60 doesn't have this register.
1861 * Hope it's OK to set it (to 0) anyway.
1862 */
1863static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1864                                         const memctl_options_t *popts)
1865{
1866        unsigned int clk_adjust;        /* Clock adjust */
1867        unsigned int ss_en = 0;         /* Source synchronous enable */
1868
1869#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
1870        /* Per FSL Application Note: AN2805 */
1871        ss_en = 1;
1872#endif
1873        if (fsl_ddr_get_version(0) >= 0x40701) {
1874                /* clk_adjust in 5-bits on T-series and LS-series */
1875                clk_adjust = (popts->clk_adjust & 0x1F) << 22;
1876        } else {
1877                /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
1878                clk_adjust = (popts->clk_adjust & 0xF) << 23;
1879        }
1880
1881        ddr->ddr_sdram_clk_cntl = (0
1882                                   | ((ss_en & 0x1) << 31)
1883                                   | clk_adjust
1884                                   );
1885        debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1886}
1887
1888/* DDR Initialization Address (DDR_INIT_ADDR) */
1889static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1890{
1891        unsigned int init_addr = 0;     /* Initialization address */
1892
1893        ddr->ddr_init_addr = init_addr;
1894}
1895
1896/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1897static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1898{
1899        unsigned int uia = 0;   /* Use initialization address */
1900        unsigned int init_ext_addr = 0; /* Initialization address */
1901
1902        ddr->ddr_init_ext_addr = (0
1903                                  | ((uia & 0x1) << 31)
1904                                  | (init_ext_addr & 0xF)
1905                                  );
1906}
1907
1908/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1909static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1910                                const memctl_options_t *popts)
1911{
1912        unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1913        unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1914        unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1915        unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1916        unsigned int trwt_mclk = 0;     /* ext_rwt */
1917        unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1918
1919#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1920        if (popts->burst_length == DDR_BL8) {
1921                /* We set BL/2 for fixed BL8 */
1922                rrt = 0;        /* BL/2 clocks */
1923                wwt = 0;        /* BL/2 clocks */
1924        } else {
1925                /* We need to set BL/2 + 2 to BC4 and OTF */
1926                rrt = 2;        /* BL/2 + 2 clocks */
1927                wwt = 2;        /* BL/2 + 2 clocks */
1928        }
1929#endif
1930#ifdef CONFIG_SYS_FSL_DDR4
1931        dll_lock = 2;   /* tDLLK = 1024 clocks */
1932#elif defined(CONFIG_SYS_FSL_DDR3)
1933        dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1934#endif
1935
1936        if (popts->trwt_override)
1937                trwt_mclk = popts->trwt;
1938
1939        ddr->timing_cfg_4 = (0
1940                             | ((rwt & 0xf) << 28)
1941                             | ((wrt & 0xf) << 24)
1942                             | ((rrt & 0xf) << 20)
1943                             | ((wwt & 0xf) << 16)
1944                             | ((trwt_mclk & 0xc) << 12)
1945                             | (dll_lock & 0x3)
1946                             );
1947        debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1948}
1949
1950/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1951static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1952{
1953        unsigned int rodt_on = 0;       /* Read to ODT on */
1954        unsigned int rodt_off = 0;      /* Read to ODT off */
1955        unsigned int wodt_on = 0;       /* Write to ODT on */
1956        unsigned int wodt_off = 0;      /* Write to ODT off */
1957
1958#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1959        unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1960                              ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1961        /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1962        if (cas_latency >= wr_lat)
1963                rodt_on = cas_latency - wr_lat + 1;
1964        rodt_off = 4;   /*  4 clocks */
1965        wodt_on = 1;    /*  1 clocks */
1966        wodt_off = 4;   /*  4 clocks */
1967#endif
1968
1969        ddr->timing_cfg_5 = (0
1970                             | ((rodt_on & 0x1f) << 24)
1971                             | ((rodt_off & 0x7) << 20)
1972                             | ((wodt_on & 0x1f) << 12)
1973                             | ((wodt_off & 0x7) << 8)
1974                             );
1975        debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1976}
1977
1978#ifdef CONFIG_SYS_FSL_DDR4
1979static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1980{
1981        unsigned int hs_caslat = 0;
1982        unsigned int hs_wrlat = 0;
1983        unsigned int hs_wrrec = 0;
1984        unsigned int hs_clkadj = 0;
1985        unsigned int hs_wrlvl_start = 0;
1986
1987        ddr->timing_cfg_6 = (0
1988                             | ((hs_caslat & 0x1f) << 24)
1989                             | ((hs_wrlat & 0x1f) << 19)
1990                             | ((hs_wrrec & 0x1f) << 12)
1991                             | ((hs_clkadj & 0x1f) << 6)
1992                             | ((hs_wrlvl_start & 0x1f) << 0)
1993                            );
1994        debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1995}
1996
1997static void set_timing_cfg_7(const unsigned int ctrl_num,
1998                             fsl_ddr_cfg_regs_t *ddr,
1999                             const memctl_options_t *popts,
2000                             const common_timing_params_t *common_dimm)
2001{
2002        unsigned int txpr, tcksre, tcksrx;
2003        unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
2004        const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
2005
2006        txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
2007        tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
2008        tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
2009
2010        if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
2011            CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
2012                /* for DDR4 only */
2013                par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1;
2014                debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);
2015        }
2016
2017        cs_to_cmd = 0;
2018
2019        if (txpr <= 200)
2020                cke_rst = 0;
2021        else if (txpr <= 256)
2022                cke_rst = 1;
2023        else if (txpr <= 512)
2024                cke_rst = 2;
2025        else
2026                cke_rst = 3;
2027
2028        if (tcksre <= 19)
2029                cksre = tcksre - 5;
2030        else
2031                cksre = 15;
2032
2033        if (tcksrx <= 19)
2034                cksrx = tcksrx - 5;
2035        else
2036                cksrx = 15;
2037
2038        ddr->timing_cfg_7 = (0
2039                             | ((cke_rst & 0x3) << 28)
2040                             | ((cksre & 0xf) << 24)
2041                             | ((cksrx & 0xf) << 20)
2042                             | ((par_lat & 0xf) << 16)
2043                             | ((cs_to_cmd & 0xf) << 4)
2044                            );
2045        debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
2046}
2047
2048static void set_timing_cfg_8(const unsigned int ctrl_num,
2049                             fsl_ddr_cfg_regs_t *ddr,
2050                             const memctl_options_t *popts,
2051                             const common_timing_params_t *common_dimm,
2052                             unsigned int cas_latency)
2053{
2054        int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
2055        unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
2056        int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
2057        int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2058                      ((ddr->timing_cfg_2 & 0x00040000) >> 14);
2059
2060        rwt_bg = cas_latency + 2 + 4 - wr_lat;
2061        if (rwt_bg < tccdl)
2062                rwt_bg = tccdl - rwt_bg;
2063        else
2064                rwt_bg = 0;
2065
2066        wrt_bg = wr_lat + 4 + 1 - cas_latency;
2067        if (wrt_bg < tccdl)
2068                wrt_bg = tccdl - wrt_bg;
2069        else
2070                wrt_bg = 0;
2071
2072        if (popts->burst_length == DDR_BL8) {
2073                rrt_bg = tccdl - 4;
2074                wwt_bg = tccdl - 4;
2075        } else {
2076                rrt_bg = tccdl - 2;
2077                wwt_bg = tccdl - 2;
2078        }
2079
2080        acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
2081        wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
2082        if (popts->otf_burst_chop_en)
2083                wrtord_bg += 2;
2084
2085        pre_all_rec = 0;
2086
2087        ddr->timing_cfg_8 = (0
2088                             | ((rwt_bg & 0xf) << 28)
2089                             | ((wrt_bg & 0xf) << 24)
2090                             | ((rrt_bg & 0xf) << 20)
2091                             | ((wwt_bg & 0xf) << 16)
2092                             | ((acttoact_bg & 0xf) << 12)
2093                             | ((wrtord_bg & 0xf) << 8)
2094                             | ((pre_all_rec & 0x1f) << 0)
2095                            );
2096
2097        debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2098}
2099
2100static void set_timing_cfg_9(const unsigned int ctrl_num,
2101                             fsl_ddr_cfg_regs_t *ddr,
2102                             const memctl_options_t *popts,
2103                             const common_timing_params_t *common_dimm)
2104{
2105        unsigned int refrec_cid_mclk = 0;
2106        unsigned int acttoact_cid_mclk = 0;
2107
2108        if (popts->package_3ds) {
2109                refrec_cid_mclk =
2110                        picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps);
2111                acttoact_cid_mclk = 4U; /* tRRDS_slr */
2112        }
2113
2114        ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16     |
2115                            (acttoact_cid_mclk & 0xf) << 8;
2116
2117        debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2118}
2119
2120/* This function needs to be called after set_ddr_sdram_cfg() is called */
2121static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2122                               const dimm_params_t *dimm_params)
2123{
2124        unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
2125        int i;
2126
2127        for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2128                if (dimm_params[i].n_ranks)
2129                        break;
2130        }
2131        if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2132                puts("DDR error: no DIMM found!\n");
2133                return;
2134        }
2135
2136        ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2137                        ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2138                        ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2139                        ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2140                        ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2141
2142        ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2143                        ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2144                        ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2145                        ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2146                        ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2147
2148        ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2149                        ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2150                        ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2151                        ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2152                        ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2153
2154        /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2155        ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2156                        ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2157                        (acc_ecc_en ? 0 :
2158                         (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2159                        dimm_params[i].dq_mapping_ors;
2160
2161        debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2162        debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2163        debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2164        debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2165}
2166static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2167                               const memctl_options_t *popts)
2168{
2169        int rd_pre;
2170
2171        rd_pre = popts->quad_rank_present ? 1 : 0;
2172
2173        ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2174        /* Disable MRS on parity error for RDIMMs */
2175        ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0;
2176
2177        if (popts->package_3ds) {       /* only 2,4,8 are supported */
2178                if ((popts->package_3ds + 1) & 0x1) {
2179                        printf("Error: Unsupported 3DS DIMM with %d die\n",
2180                               popts->package_3ds + 1);
2181                } else {
2182                        ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1)
2183                                                << 4;
2184                }
2185        }
2186
2187        debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2188}
2189#endif  /* CONFIG_SYS_FSL_DDR4 */
2190
2191/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2192static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2193{
2194        unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2195        /* Normal Operation Full Calibration Time (tZQoper) */
2196        unsigned int zqoper = 0;
2197        /* Normal Operation Short Calibration Time (tZQCS) */
2198        unsigned int zqcs = 0;
2199#ifdef CONFIG_SYS_FSL_DDR4
2200        unsigned int zqcs_init;
2201#endif
2202
2203        if (zq_en) {
2204#ifdef CONFIG_SYS_FSL_DDR4
2205                zqinit = 10;    /* 1024 clocks */
2206                zqoper = 9;     /* 512 clocks */
2207                zqcs = 7;       /* 128 clocks */
2208                zqcs_init = 5;  /* 1024 refresh sequences */
2209#else
2210                zqinit = 9;     /* 512 clocks */
2211                zqoper = 8;     /* 256 clocks */
2212                zqcs = 6;       /* 64 clocks */
2213#endif
2214        }
2215
2216        ddr->ddr_zq_cntl = (0
2217                            | ((zq_en & 0x1) << 31)
2218                            | ((zqinit & 0xF) << 24)
2219                            | ((zqoper & 0xF) << 16)
2220                            | ((zqcs & 0xF) << 8)
2221#ifdef CONFIG_SYS_FSL_DDR4
2222                            | ((zqcs_init & 0xF) << 0)
2223#endif
2224                            );
2225        debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2226}
2227
2228/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2229static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2230                                const memctl_options_t *popts)
2231{
2232        /*
2233         * First DQS pulse rising edge after margining mode
2234         * is programmed (tWL_MRD)
2235         */
2236        unsigned int wrlvl_mrd = 0;
2237        /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2238        unsigned int wrlvl_odten = 0;
2239        /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2240        unsigned int wrlvl_dqsen = 0;
2241        /* WRLVL_SMPL: Write leveling sample time */
2242        unsigned int wrlvl_smpl = 0;
2243        /* WRLVL_WLR: Write leveling repeition time */
2244        unsigned int wrlvl_wlr = 0;
2245        /* WRLVL_START: Write leveling start time */
2246        unsigned int wrlvl_start = 0;
2247
2248        /* suggest enable write leveling for DDR3 due to fly-by topology */
2249        if (wrlvl_en) {
2250                /* tWL_MRD min = 40 nCK, we set it 64 */
2251                wrlvl_mrd = 0x6;
2252                /* tWL_ODTEN 128 */
2253                wrlvl_odten = 0x7;
2254                /* tWL_DQSEN min = 25 nCK, we set it 32 */
2255                wrlvl_dqsen = 0x5;
2256                /*
2257                 * Write leveling sample time at least need 6 clocks
2258                 * higher than tWLO to allow enough time for progagation
2259                 * delay and sampling the prime data bits.
2260                 */
2261                wrlvl_smpl = 0xf;
2262                /*
2263                 * Write leveling repetition time
2264                 * at least tWLO + 6 clocks clocks
2265                 * we set it 64
2266                 */
2267                wrlvl_wlr = 0x6;
2268                /*
2269                 * Write leveling start time
2270                 * The value use for the DQS_ADJUST for the first sample
2271                 * when write leveling is enabled. It probably needs to be
2272                 * overridden per platform.
2273                 */
2274                wrlvl_start = 0x8;
2275                /*
2276                 * Override the write leveling sample and start time
2277                 * according to specific board
2278                 */
2279                if (popts->wrlvl_override) {
2280                        wrlvl_smpl = popts->wrlvl_sample;
2281                        wrlvl_start = popts->wrlvl_start;
2282                }
2283        }
2284
2285        ddr->ddr_wrlvl_cntl = (0
2286                               | ((wrlvl_en & 0x1) << 31)
2287                               | ((wrlvl_mrd & 0x7) << 24)
2288                               | ((wrlvl_odten & 0x7) << 20)
2289                               | ((wrlvl_dqsen & 0x7) << 16)
2290                               | ((wrlvl_smpl & 0xf) << 12)
2291                               | ((wrlvl_wlr & 0x7) << 8)
2292                               | ((wrlvl_start & 0x1F) << 0)
2293                               );
2294        debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2295        ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2296        debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2297        ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2298        debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2299
2300}
2301
2302/* DDR Self Refresh Counter (DDR_SR_CNTR) */
2303static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2304{
2305        /* Self Refresh Idle Threshold */
2306        ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2307}
2308
2309static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2310{
2311        if (popts->addr_hash) {
2312                ddr->ddr_eor = 0x40000000;      /* address hash enable */
2313                puts("Address hashing enabled.\n");
2314        }
2315}
2316
2317static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2318{
2319        ddr->ddr_cdr1 = popts->ddr_cdr1;
2320        debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2321}
2322
2323static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2324{
2325        ddr->ddr_cdr2 = popts->ddr_cdr2;
2326        debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2327}
2328
2329unsigned int
2330check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2331{
2332        unsigned int res = 0;
2333
2334        /*
2335         * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2336         * not set at the same time.
2337         */
2338        if (ddr->ddr_sdram_cfg & 0x10000000
2339            && ddr->ddr_sdram_cfg & 0x00008000) {
2340                printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2341                                " should not be set at the same time.\n");
2342                res++;
2343        }
2344
2345        return res;
2346}
2347
2348unsigned int
2349compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2350                               const memctl_options_t *popts,
2351                               fsl_ddr_cfg_regs_t *ddr,
2352                               const common_timing_params_t *common_dimm,
2353                               const dimm_params_t *dimm_params,
2354                               unsigned int dbw_cap_adj,
2355                               unsigned int size_only)
2356{
2357        unsigned int i;
2358        unsigned int cas_latency;
2359        unsigned int additive_latency;
2360        unsigned int sr_it;
2361        unsigned int zq_en;
2362        unsigned int wrlvl_en;
2363        unsigned int ip_rev = 0;
2364        unsigned int unq_mrs_en = 0;
2365        int cs_en = 1;
2366
2367        memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2368
2369        if (common_dimm == NULL) {
2370                printf("Error: subset DIMM params struct null pointer\n");
2371                return 1;
2372        }
2373
2374        /*
2375         * Process overrides first.
2376         *
2377         * FIXME: somehow add dereated caslat to this
2378         */
2379        cas_latency = (popts->cas_latency_override)
2380                ? popts->cas_latency_override_value
2381                : common_dimm->lowest_common_spd_caslat;
2382
2383        additive_latency = (popts->additive_latency_override)
2384                ? popts->additive_latency_override_value
2385                : common_dimm->additive_latency;
2386
2387        sr_it = (popts->auto_self_refresh_en)
2388                ? popts->sr_it
2389                : 0;
2390        /* ZQ calibration */
2391        zq_en = (popts->zq_en) ? 1 : 0;
2392        /* write leveling */
2393        wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2394
2395        /* Chip Select Memory Bounds (CSn_BNDS) */
2396        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2397                unsigned long long ea, sa;
2398                unsigned int cs_per_dimm
2399                        = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2400                unsigned int dimm_number
2401                        = i / cs_per_dimm;
2402                unsigned long long rank_density
2403                        = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2404
2405                if (dimm_params[dimm_number].n_ranks == 0) {
2406                        debug("Skipping setup of CS%u "
2407                                "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2408                        continue;
2409                }
2410                if (popts->memctl_interleaving) {
2411                        switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2412                        case FSL_DDR_CS0_CS1_CS2_CS3:
2413                                break;
2414                        case FSL_DDR_CS0_CS1:
2415                        case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2416                                if (i > 1)
2417                                        cs_en = 0;
2418                                break;
2419                        case FSL_DDR_CS2_CS3:
2420                        default:
2421                                if (i > 0)
2422                                        cs_en = 0;
2423                                break;
2424                        }
2425                        sa = common_dimm->base_address;
2426                        ea = sa + common_dimm->total_mem - 1;
2427                } else if (!popts->memctl_interleaving) {
2428                        /*
2429                         * If memory interleaving between controllers is NOT
2430                         * enabled, the starting address for each memory
2431                         * controller is distinct.  However, because rank
2432                         * interleaving is enabled, the starting and ending
2433                         * addresses of the total memory on that memory
2434                         * controller needs to be programmed into its
2435                         * respective CS0_BNDS.
2436                         */
2437                        switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2438                        case FSL_DDR_CS0_CS1_CS2_CS3:
2439                                sa = common_dimm->base_address;
2440                                ea = sa + common_dimm->total_mem - 1;
2441                                break;
2442                        case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2443                                if ((i >= 2) && (dimm_number == 0)) {
2444                                        sa = dimm_params[dimm_number].base_address +
2445                                              2 * rank_density;
2446                                        ea = sa + 2 * rank_density - 1;
2447                                } else {
2448                                        sa = dimm_params[dimm_number].base_address;
2449                                        ea = sa + 2 * rank_density - 1;
2450                                }
2451                                break;
2452                        case FSL_DDR_CS0_CS1:
2453                                if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2454                                        sa = dimm_params[dimm_number].base_address;
2455                                        ea = sa + rank_density - 1;
2456                                        if (i != 1)
2457                                                sa += (i % cs_per_dimm) * rank_density;
2458                                        ea += (i % cs_per_dimm) * rank_density;
2459                                } else {
2460                                        sa = 0;
2461                                        ea = 0;
2462                                }
2463                                if (i == 0)
2464                                        ea += rank_density;
2465                                break;
2466                        case FSL_DDR_CS2_CS3:
2467                                if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2468                                        sa = dimm_params[dimm_number].base_address;
2469                                        ea = sa + rank_density - 1;
2470                                        if (i != 3)
2471                                                sa += (i % cs_per_dimm) * rank_density;
2472                                        ea += (i % cs_per_dimm) * rank_density;
2473                                } else {
2474                                        sa = 0;
2475                                        ea = 0;
2476                                }
2477                                if (i == 2)
2478                                        ea += (rank_density >> dbw_cap_adj);
2479                                break;
2480                        default:  /* No bank(chip-select) interleaving */
2481                                sa = dimm_params[dimm_number].base_address;
2482                                ea = sa + rank_density - 1;
2483                                if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2484                                        sa += (i % cs_per_dimm) * rank_density;
2485                                        ea += (i % cs_per_dimm) * rank_density;
2486                                } else {
2487                                        sa = 0;
2488                                        ea = 0;
2489                                }
2490                                break;
2491                        }
2492                }
2493
2494                sa >>= 24;
2495                ea >>= 24;
2496
2497                if (cs_en) {
2498                        ddr->cs[i].bnds = (0
2499                                | ((sa & 0xffff) << 16) /* starting address */
2500                                | ((ea & 0xffff) << 0)  /* ending address */
2501                                );
2502                } else {
2503                        /* setting bnds to 0xffffffff for inactive CS */
2504                        ddr->cs[i].bnds = 0xffffffff;
2505                }
2506
2507                debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2508                set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2509                set_csn_config_2(i, ddr);
2510        }
2511
2512        /*
2513         * In the case we only need to compute the ddr sdram size, we only need
2514         * to set csn registers, so return from here.
2515         */
2516        if (size_only)
2517                return 0;
2518
2519        set_ddr_eor(ddr, popts);
2520
2521#if !defined(CONFIG_SYS_FSL_DDR1)
2522        set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2523#endif
2524
2525        set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2526                         additive_latency);
2527        set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2528        set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2529                         cas_latency, additive_latency);
2530
2531        set_ddr_cdr1(ddr, popts);
2532        set_ddr_cdr2(ddr, popts);
2533        set_ddr_sdram_cfg(ddr, popts, common_dimm);
2534        ip_rev = fsl_ddr_get_version(ctrl_num);
2535        if (ip_rev > 0x40400)
2536                unq_mrs_en = 1;
2537
2538        if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2539                ddr->debug[18] = popts->cswl_override;
2540
2541        set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2542        set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2543                           cas_latency, additive_latency, unq_mrs_en);
2544        set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2545#ifdef CONFIG_SYS_FSL_DDR4
2546        set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2547        set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2548#endif
2549        set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm);
2550
2551        set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2552        set_ddr_data_init(ddr);
2553        set_ddr_sdram_clk_cntl(ddr, popts);
2554        set_ddr_init_addr(ddr);
2555        set_ddr_init_ext_addr(ddr);
2556        set_timing_cfg_4(ddr, popts);
2557        set_timing_cfg_5(ddr, cas_latency);
2558#ifdef CONFIG_SYS_FSL_DDR4
2559        set_ddr_sdram_cfg_3(ddr, popts);
2560        set_timing_cfg_6(ddr);
2561        set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm);
2562        set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2563        set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm);
2564        set_ddr_dq_mapping(ddr, dimm_params);
2565#endif
2566
2567        set_ddr_zq_cntl(ddr, zq_en);
2568        set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2569
2570        set_ddr_sr_cntr(ddr, sr_it);
2571
2572#ifdef CONFIG_SYS_FSL_DDR_EMU
2573        /* disble DDR training for emulator */
2574        ddr->debug[2] = 0x00000400;
2575        ddr->debug[4] = 0xff800800;
2576        ddr->debug[5] = 0x08000800;
2577        ddr->debug[6] = 0x08000800;
2578        ddr->debug[7] = 0x08000800;
2579        ddr->debug[8] = 0x08000800;
2580#endif
2581#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2582        if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2583                ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2584#endif
2585
2586#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2587        if (popts->cpo_sample)
2588                ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
2589                                  popts->cpo_sample;
2590#endif
2591
2592        return check_fsl_memctl_config_regs(ddr);
2593}
2594
2595#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2596/*
2597 * This additional workaround of A009942 checks the condition to determine if
2598 * the CPO value set by the existing A009942 workaround needs to be updated.
2599 * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
2600 * expected optimal value, the optimal value is highly board dependent.
2601 */
2602void erratum_a009942_check_cpo(void)
2603{
2604        struct ccsr_ddr __iomem *ddr =
2605                (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
2606        u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
2607        u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
2608        u32 cpo_max = cpo_min;
2609        u32 sdram_cfg, i, tmp, lanes, ddr_type;
2610        bool update_cpo = false, has_ecc = false;
2611
2612        sdram_cfg = ddr_in32(&ddr->sdram_cfg);
2613        if (sdram_cfg & SDRAM_CFG_32_BE)
2614                lanes = 4;
2615        else if (sdram_cfg & SDRAM_CFG_16_BE)
2616                lanes = 2;
2617        else
2618                lanes = 8;
2619
2620        if (sdram_cfg & SDRAM_CFG_ECC_EN)
2621                has_ecc = true;
2622
2623        /* determine the maximum and minimum CPO values */
2624        for (i = 9; i < 9 + lanes / 2; i++) {
2625                cpo = ddr_in32(&ddr->debug[i]);
2626                cpo_e = cpo >> 24;
2627                cpo_o = (cpo >> 8) & 0xff;
2628                tmp = min(cpo_e, cpo_o);
2629                if (tmp < cpo_min)
2630                        cpo_min = tmp;
2631                tmp = max(cpo_e, cpo_o);
2632                if (tmp > cpo_max)
2633                        cpo_max = tmp;
2634        }
2635
2636        if (has_ecc) {
2637                cpo = ddr_in32(&ddr->debug[13]);
2638                cpo = cpo >> 24;
2639                if (cpo < cpo_min)
2640                        cpo_min = cpo;
2641                if (cpo > cpo_max)
2642                        cpo_max = cpo;
2643        }
2644
2645        cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
2646        cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
2647        debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
2648              cpo_target);
2649        debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
2650
2651        ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
2652                    SDRAM_CFG_SDRAM_TYPE_SHIFT;
2653        if (ddr_type == SDRAM_TYPE_DDR4)
2654                update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
2655        else if (ddr_type == SDRAM_TYPE_DDR3)
2656                update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
2657
2658        if (update_cpo) {
2659                printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
2660                printf("in <board>/ddr.c to optimize cpo\n");
2661        }
2662}
2663#endif
2664