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12#include <common.h>
13#include <dm.h>
14#include <i2c.h>
15#include <fsl_ddr_sdram.h>
16#include <fsl_ddr.h>
17#include <init.h>
18#include <log.h>
19#include <asm/bitops.h>
20
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28
29#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
30#ifdef CONFIG_MPC83xx
31#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
32#else
33#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
34#endif
35#endif
36
37#ifdef CONFIG_PPC
38#include <asm/fsl_law.h>
39
40void fsl_ddr_set_lawbar(
41 const common_timing_params_t *memctl_common_params,
42 unsigned int memctl_interleaved,
43 unsigned int ctrl_num);
44#endif
45
46void fsl_ddr_set_intl3r(const unsigned int granule_size);
47#if defined(SPD_EEPROM_ADDRESS) || \
48 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
49 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
50#if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
51u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
52 [0][0] = SPD_EEPROM_ADDRESS,
53};
54#elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
55u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
56 [0][0] = SPD_EEPROM_ADDRESS1,
57 [0][1] = SPD_EEPROM_ADDRESS2,
58};
59#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
60u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
61 [0][0] = SPD_EEPROM_ADDRESS1,
62 [1][0] = SPD_EEPROM_ADDRESS2,
63};
64#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
65u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
66 [0][0] = SPD_EEPROM_ADDRESS1,
67 [0][1] = SPD_EEPROM_ADDRESS2,
68 [1][0] = SPD_EEPROM_ADDRESS3,
69 [1][1] = SPD_EEPROM_ADDRESS4,
70};
71#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
72u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
73 [0][0] = SPD_EEPROM_ADDRESS1,
74 [1][0] = SPD_EEPROM_ADDRESS2,
75 [2][0] = SPD_EEPROM_ADDRESS3,
76};
77#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
78u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
79 [0][0] = SPD_EEPROM_ADDRESS1,
80 [0][1] = SPD_EEPROM_ADDRESS2,
81 [1][0] = SPD_EEPROM_ADDRESS3,
82 [1][1] = SPD_EEPROM_ADDRESS4,
83 [2][0] = SPD_EEPROM_ADDRESS5,
84 [2][1] = SPD_EEPROM_ADDRESS6,
85};
86
87#endif
88
89#if defined(CONFIG_DM_I2C)
90#define DEV_TYPE struct udevice
91#else
92
93struct ludevice {
94 u8 chip;
95};
96
97#define DEV_TYPE struct ludevice
98
99#endif
100
101#define SPD_SPA0_ADDRESS 0x36
102#define SPD_SPA1_ADDRESS 0x37
103
104static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr,
105 int alen, uint8_t *buf, int len)
106{
107 int ret;
108
109#ifdef CONFIG_DM_I2C
110 ret = dm_i2c_read(dev, 0, buf, len);
111#else
112 ret = i2c_read(dev->chip, addr, alen, buf, len);
113#endif
114
115 return ret;
116}
117
118#ifdef CONFIG_SYS_FSL_DDR4
119static int ddr_i2c_dummy_write(unsigned int chip_addr)
120{
121 uint8_t buf = 0;
122
123#ifdef CONFIG_DM_I2C
124 struct udevice *dev;
125 int ret;
126
127 ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr,
128 1, &dev);
129 if (ret) {
130 printf("%s: Cannot find udev for a bus %d\n", __func__,
131 CONFIG_SYS_SPD_BUS_NUM);
132 return ret;
133 }
134
135 return dm_i2c_write(dev, 0, &buf, 1);
136#else
137 return i2c_write(chip_addr, 0, 1, &buf, 1);
138#endif
139
140 return 0;
141}
142#endif
143
144static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
145{
146 int ret;
147 DEV_TYPE *dev;
148
149#if defined(CONFIG_DM_I2C)
150 ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
151 1, &dev);
152 if (ret) {
153 printf("%s: Cannot find udev for a bus %d\n", __func__,
154 CONFIG_SYS_SPD_BUS_NUM);
155 return;
156 }
157#else
158 struct ludevice ldev = {
159 .chip = i2c_address,
160 };
161 dev = &ldev;
162
163 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
164#endif
165
166#ifdef CONFIG_SYS_FSL_DDR4
167
168
169
170
171
172
173 ddr_i2c_dummy_write(SPD_SPA0_ADDRESS);
174 ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256);
175 if (!ret) {
176 ddr_i2c_dummy_write(SPD_SPA1_ADDRESS);
177 ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256),
178 min(256,
179 (int)sizeof(generic_spd_eeprom_t)
180 - 256));
181 }
182
183#else
184 ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd,
185 sizeof(generic_spd_eeprom_t));
186#endif
187
188 if (ret) {
189 if (i2c_address ==
190#ifdef SPD_EEPROM_ADDRESS
191 SPD_EEPROM_ADDRESS
192#elif defined(SPD_EEPROM_ADDRESS1)
193 SPD_EEPROM_ADDRESS1
194#endif
195 ) {
196 printf("DDR: failed to read SPD from address %u\n",
197 i2c_address);
198 } else {
199 debug("DDR: failed to read SPD from address %u\n",
200 i2c_address);
201 }
202 memset(spd, 0, sizeof(generic_spd_eeprom_t));
203 }
204}
205
206__attribute__((weak, alias("__get_spd")))
207void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
208
209
210__weak void update_spd_address(unsigned int ctrl_num,
211 unsigned int slot,
212 unsigned int *addr)
213{
214}
215
216void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
217 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
218{
219 unsigned int i;
220 unsigned int i2c_address = 0;
221
222 if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
223 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
224 return;
225 }
226
227 for (i = 0; i < dimm_slots_per_ctrl; i++) {
228 i2c_address = spd_i2c_addr[ctrl_num][i];
229 update_spd_address(ctrl_num, i, &i2c_address);
230 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
231 }
232}
233#else
234void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
235 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
236{
237}
238#endif
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284
285const char *step_string_tbl[] = {
286 "STEP_GET_SPD",
287 "STEP_COMPUTE_DIMM_PARMS",
288 "STEP_COMPUTE_COMMON_PARMS",
289 "STEP_GATHER_OPTS",
290 "STEP_ASSIGN_ADDRESSES",
291 "STEP_COMPUTE_REGS",
292 "STEP_PROGRAM_REGS",
293 "STEP_ALL"
294};
295
296const char * step_to_string(unsigned int step) {
297
298 unsigned int s = __ilog2(step);
299
300 if ((1 << s) != step)
301 return step_string_tbl[7];
302
303 if (s >= ARRAY_SIZE(step_string_tbl)) {
304 printf("Error for the step in %s\n", __func__);
305 s = 0;
306 }
307
308 return step_string_tbl[s];
309}
310
311static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
312 unsigned int dbw_cap_adj[])
313{
314 unsigned int i, j;
315 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
316 unsigned long long rank_density, ctlr_density = 0;
317 unsigned int first_ctrl = pinfo->first_ctrl;
318 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
319
320
321
322
323
324
325
326 for (i = first_ctrl; i <= last_ctrl; i++) {
327 unsigned int found = 0;
328
329 switch (pinfo->memctl_opts[i].data_bus_width) {
330 case 2:
331
332 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
333 unsigned int dw;
334 if (!pinfo->dimm_params[i][j].n_ranks)
335 continue;
336 dw = pinfo->dimm_params[i][j].primary_sdram_width;
337 if ((dw == 72 || dw == 64)) {
338 dbw_cap_adj[i] = 2;
339 break;
340 } else if ((dw == 40 || dw == 32)) {
341 dbw_cap_adj[i] = 1;
342 break;
343 }
344 }
345 break;
346
347 case 1:
348
349 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
350 unsigned int dw;
351 dw = pinfo->dimm_params[i][j].data_width;
352 if (pinfo->dimm_params[i][j].n_ranks
353 && (dw == 72 || dw == 64)) {
354
355
356
357
358
359 found = 1;
360 break;
361 }
362 }
363 if (found) {
364 dbw_cap_adj[i] = 1;
365 }
366 break;
367
368 case 0:
369
370 break;
371
372 default:
373 printf("unexpected data bus width "
374 "specified controller %u\n", i);
375 return 1;
376 }
377 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
378 }
379
380 current_mem_base = pinfo->mem_base;
381 total_mem = 0;
382 if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
383 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
384 dbw_cap_adj[first_ctrl];
385 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
386 FSL_DDR_CS0_CS1_CS2_CS3) {
387 case FSL_DDR_CS0_CS1_CS2_CS3:
388 ctlr_density = 4 * rank_density;
389 break;
390 case FSL_DDR_CS0_CS1:
391 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
392 ctlr_density = 2 * rank_density;
393 break;
394 case FSL_DDR_CS2_CS3:
395 default:
396 ctlr_density = rank_density;
397 break;
398 }
399 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
400 rank_density, ctlr_density);
401 for (i = first_ctrl; i <= last_ctrl; i++) {
402 if (pinfo->memctl_opts[i].memctl_interleaving) {
403 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
404 case FSL_DDR_256B_INTERLEAVING:
405 case FSL_DDR_CACHE_LINE_INTERLEAVING:
406 case FSL_DDR_PAGE_INTERLEAVING:
407 case FSL_DDR_BANK_INTERLEAVING:
408 case FSL_DDR_SUPERBANK_INTERLEAVING:
409 total_ctlr_mem = 2 * ctlr_density;
410 break;
411 case FSL_DDR_3WAY_1KB_INTERLEAVING:
412 case FSL_DDR_3WAY_4KB_INTERLEAVING:
413 case FSL_DDR_3WAY_8KB_INTERLEAVING:
414 total_ctlr_mem = 3 * ctlr_density;
415 break;
416 case FSL_DDR_4WAY_1KB_INTERLEAVING:
417 case FSL_DDR_4WAY_4KB_INTERLEAVING:
418 case FSL_DDR_4WAY_8KB_INTERLEAVING:
419 total_ctlr_mem = 4 * ctlr_density;
420 break;
421 default:
422 panic("Unknown interleaving mode");
423 }
424 pinfo->common_timing_params[i].base_address =
425 current_mem_base;
426 pinfo->common_timing_params[i].total_mem =
427 total_ctlr_mem;
428 total_mem = current_mem_base + total_ctlr_mem;
429 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
430 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
431 } else {
432
433 current_mem_base = total_mem;
434 total_ctlr_mem = 0;
435 pinfo->common_timing_params[i].base_address =
436 current_mem_base;
437 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
438 unsigned long long cap =
439 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
440 pinfo->dimm_params[i][j].base_address =
441 current_mem_base;
442 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
443 current_mem_base += cap;
444 total_ctlr_mem += cap;
445 }
446 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
447 pinfo->common_timing_params[i].total_mem =
448 total_ctlr_mem;
449 total_mem += total_ctlr_mem;
450 }
451 }
452 } else {
453
454
455
456
457 for (i = first_ctrl; i <= last_ctrl; i++) {
458 total_ctlr_mem = 0;
459 pinfo->common_timing_params[i].base_address =
460 current_mem_base;
461 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
462
463 unsigned long long cap =
464 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
465 pinfo->dimm_params[i][j].base_address =
466 current_mem_base;
467 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
468 current_mem_base += cap;
469 total_ctlr_mem += cap;
470 }
471 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
472 pinfo->common_timing_params[i].total_mem =
473 total_ctlr_mem;
474 total_mem += total_ctlr_mem;
475 }
476 }
477 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
478
479 return total_mem;
480}
481
482
483__attribute__((weak, alias("__step_assign_addresses")))
484unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
485 unsigned int dbw_cap_adj[]);
486
487unsigned long long
488fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
489 unsigned int size_only)
490{
491 unsigned int i, j;
492 unsigned long long total_mem = 0;
493 int assert_reset = 0;
494 unsigned int first_ctrl = pinfo->first_ctrl;
495 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
496 __maybe_unused int retval;
497 __maybe_unused bool goodspd = false;
498 __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
499
500 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
501 common_timing_params_t *timing_params = pinfo->common_timing_params;
502 if (pinfo->board_need_mem_reset)
503 assert_reset = pinfo->board_need_mem_reset();
504
505
506 unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
507
508 for (i = first_ctrl; i <= last_ctrl; i++)
509 dbw_capacity_adjust[i] = 0;
510
511 debug("starting at step %u (%s)\n",
512 start_step, step_to_string(start_step));
513
514 switch (start_step) {
515 case STEP_GET_SPD:
516#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
517
518 for (i = first_ctrl; i <= last_ctrl; i++) {
519 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
520 dimm_slots_per_ctrl);
521 }
522
523 case STEP_COMPUTE_DIMM_PARMS:
524
525
526 for (i = first_ctrl; i <= last_ctrl; i++) {
527 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
528 generic_spd_eeprom_t *spd =
529 &(pinfo->spd_installed_dimms[i][j]);
530 dimm_params_t *pdimm =
531 &(pinfo->dimm_params[i][j]);
532 retval = compute_dimm_parameters(
533 i, spd, pdimm, j);
534#ifdef CONFIG_SYS_DDR_RAW_TIMING
535 if (!j && retval) {
536 printf("SPD error on controller %d! "
537 "Trying fallback to raw timing "
538 "calculation\n", i);
539 retval = fsl_ddr_get_dimm_params(pdimm,
540 i, j);
541 }
542#else
543 if (retval == 2) {
544 printf("Error: compute_dimm_parameters"
545 " non-zero returned FATAL value "
546 "for memctl=%u dimm=%u\n", i, j);
547 return 0;
548 }
549#endif
550 if (retval) {
551 debug("Warning: compute_dimm_parameters"
552 " non-zero return value for memctl=%u "
553 "dimm=%u\n", i, j);
554 } else {
555 goodspd = true;
556 }
557 }
558 }
559 if (!goodspd) {
560
561
562
563
564
565
566 if (first_ctrl == 0)
567 printf("Error: No valid SPD detected.\n");
568
569 return 0;
570 }
571#elif defined(CONFIG_SYS_DDR_RAW_TIMING)
572 case STEP_COMPUTE_DIMM_PARMS:
573 for (i = first_ctrl; i <= last_ctrl; i++) {
574 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
575 dimm_params_t *pdimm =
576 &(pinfo->dimm_params[i][j]);
577 fsl_ddr_get_dimm_params(pdimm, i, j);
578 }
579 }
580 debug("Filling dimm parameters from board specific file\n");
581#endif
582 case STEP_COMPUTE_COMMON_PARMS:
583
584
585
586
587 for (i = first_ctrl; i <= last_ctrl; i++) {
588 debug("Computing lowest common DIMM"
589 " parameters for memctl=%u\n", i);
590 compute_lowest_common_dimm_parameters
591 (i,
592 pinfo->dimm_params[i],
593 &timing_params[i],
594 CONFIG_DIMM_SLOTS_PER_CTLR);
595 }
596
597 case STEP_GATHER_OPTS:
598
599 for (i = first_ctrl; i <= last_ctrl; i++) {
600 debug("Reloading memory controller "
601 "configuration options for memctl=%u\n", i);
602
603
604
605
606
607
608 populate_memctl_options(
609 &timing_params[i],
610 &pinfo->memctl_opts[i],
611 pinfo->dimm_params[i], i);
612
613
614
615
616
617
618 if (timing_params[i].all_dimms_registered)
619 assert_reset = 1;
620 }
621 if (assert_reset && !size_only) {
622 if (pinfo->board_mem_reset) {
623 debug("Asserting mem reset\n");
624 pinfo->board_mem_reset();
625 } else {
626 debug("Asserting mem reset missing\n");
627 }
628 }
629
630 case STEP_ASSIGN_ADDRESSES:
631
632 check_interleaving_options(pinfo);
633 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
634 debug("Total mem %llu assigned\n", total_mem);
635
636 case STEP_COMPUTE_REGS:
637
638 debug("FSL Memory ctrl register computation\n");
639 for (i = first_ctrl; i <= last_ctrl; i++) {
640 if (timing_params[i].ndimms_present == 0) {
641 memset(&ddr_reg[i], 0,
642 sizeof(fsl_ddr_cfg_regs_t));
643 continue;
644 }
645
646 compute_fsl_memctl_config_regs
647 (i,
648 &pinfo->memctl_opts[i],
649 &ddr_reg[i], &timing_params[i],
650 pinfo->dimm_params[i],
651 dbw_capacity_adjust[i],
652 size_only);
653 }
654
655 default:
656 break;
657 }
658
659 {
660
661
662
663
664
665
666 unsigned int max_end = 0;
667
668 for (i = first_ctrl; i <= last_ctrl; i++) {
669 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
670 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
671 if (reg->cs[j].config & 0x80000000) {
672 unsigned int end;
673
674
675
676
677 if (reg->cs[j].bnds == 0xffffffff)
678 continue;
679 end = reg->cs[j].bnds & 0xffff;
680 if (end > max_end) {
681 max_end = end;
682 }
683 }
684 }
685 }
686
687 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
688 0xFFFFFFULL) - pinfo->mem_base;
689 }
690
691 return total_mem;
692}
693
694phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
695{
696 unsigned int i, first_ctrl, last_ctrl;
697#ifdef CONFIG_PPC
698 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
699#endif
700 unsigned long long total_memory;
701 int deassert_reset = 0;
702
703 first_ctrl = pinfo->first_ctrl;
704 last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
705
706
707#ifdef CONFIG_FSL_DDR_INTERACTIVE
708 if (tstc() && (getchar() == 'd')) {
709 total_memory = fsl_ddr_interactive(pinfo, 0);
710 } else if (fsl_ddr_interactive_env_var_exists()) {
711 total_memory = fsl_ddr_interactive(pinfo, 1);
712 } else
713#endif
714 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
715
716
717 switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
718 case FSL_DDR_3WAY_1KB_INTERLEAVING:
719 case FSL_DDR_3WAY_4KB_INTERLEAVING:
720 case FSL_DDR_3WAY_8KB_INTERLEAVING:
721 fsl_ddr_set_intl3r(
722 pinfo->memctl_opts[first_ctrl].
723 memctl_interleaving_mode);
724 break;
725 default:
726 break;
727 }
728
729
730
731
732
733
734
735
736
737
738
739 if (pinfo->board_need_mem_reset)
740 deassert_reset = pinfo->board_need_mem_reset();
741 for (i = first_ctrl; i <= last_ctrl; i++) {
742 if (pinfo->common_timing_params[i].all_dimms_registered)
743 deassert_reset = 1;
744 }
745 for (i = first_ctrl; i <= last_ctrl; i++) {
746 debug("Programming controller %u\n", i);
747 if (pinfo->common_timing_params[i].ndimms_present == 0) {
748 debug("No dimms present on controller %u; "
749 "skipping programming\n", i);
750 continue;
751 }
752
753
754
755
756 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
757 deassert_reset ? 1 : 0);
758 }
759 if (deassert_reset) {
760
761 if (pinfo->board_mem_de_reset) {
762 debug("Deasserting mem reset\n");
763 pinfo->board_mem_de_reset();
764 } else {
765 debug("Deasserting mem reset missing\n");
766 }
767 for (i = first_ctrl; i <= last_ctrl; i++) {
768
769 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
770 i, 2);
771 }
772 }
773
774#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
775 fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
776#endif
777
778#ifdef CONFIG_PPC
779
780 for (i = first_ctrl; i <= last_ctrl; i++) {
781 if (pinfo->memctl_opts[i].memctl_interleaving) {
782 switch (pinfo->memctl_opts[i].
783 memctl_interleaving_mode) {
784 case FSL_DDR_CACHE_LINE_INTERLEAVING:
785 case FSL_DDR_PAGE_INTERLEAVING:
786 case FSL_DDR_BANK_INTERLEAVING:
787 case FSL_DDR_SUPERBANK_INTERLEAVING:
788 if (i % 2)
789 break;
790 if (i == 0) {
791 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
792 fsl_ddr_set_lawbar(
793 &pinfo->common_timing_params[i],
794 law_memctl, i);
795 }
796#if CONFIG_SYS_NUM_DDR_CTLRS > 3
797 else if (i == 2) {
798 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
799 fsl_ddr_set_lawbar(
800 &pinfo->common_timing_params[i],
801 law_memctl, i);
802 }
803#endif
804 break;
805 case FSL_DDR_3WAY_1KB_INTERLEAVING:
806 case FSL_DDR_3WAY_4KB_INTERLEAVING:
807 case FSL_DDR_3WAY_8KB_INTERLEAVING:
808 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
809 if (i == 0) {
810 fsl_ddr_set_lawbar(
811 &pinfo->common_timing_params[i],
812 law_memctl, i);
813 }
814 break;
815 case FSL_DDR_4WAY_1KB_INTERLEAVING:
816 case FSL_DDR_4WAY_4KB_INTERLEAVING:
817 case FSL_DDR_4WAY_8KB_INTERLEAVING:
818 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
819 if (i == 0)
820 fsl_ddr_set_lawbar(
821 &pinfo->common_timing_params[i],
822 law_memctl, i);
823
824 break;
825 default:
826 break;
827 }
828 } else {
829 switch (i) {
830 case 0:
831 law_memctl = LAW_TRGT_IF_DDR_1;
832 break;
833 case 1:
834 law_memctl = LAW_TRGT_IF_DDR_2;
835 break;
836 case 2:
837 law_memctl = LAW_TRGT_IF_DDR_3;
838 break;
839 case 3:
840 law_memctl = LAW_TRGT_IF_DDR_4;
841 break;
842 default:
843 break;
844 }
845 fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
846 law_memctl, i);
847 }
848 }
849#endif
850
851 debug("total_memory by %s = %llu\n", __func__, total_memory);
852
853#if !defined(CONFIG_PHYS_64BIT)
854
855 if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
856 puts("Detected ");
857 print_size(total_memory, " of memory\n");
858 printf(" This U-Boot only supports < 4G of DDR\n");
859 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
860 printf(" ");
861 total_memory = CONFIG_MAX_MEM_MAPPED;
862 }
863#endif
864
865 return total_memory;
866}
867
868
869
870
871
872
873
874phys_size_t fsl_ddr_sdram(void)
875{
876 fsl_ddr_info_t info;
877
878
879 memset(&info, 0, sizeof(fsl_ddr_info_t));
880 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
881 info.first_ctrl = 0;
882 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
883 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
884 info.board_need_mem_reset = board_need_mem_reset;
885 info.board_mem_reset = board_assert_mem_reset;
886 info.board_mem_de_reset = board_deassert_mem_reset;
887 remove_unused_controllers(&info);
888
889 return __fsl_ddr_sdram(&info);
890}
891
892#ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
893phys_size_t fsl_other_ddr_sdram(unsigned long long base,
894 unsigned int first_ctrl,
895 unsigned int num_ctrls,
896 unsigned int dimm_slots_per_ctrl,
897 int (*board_need_reset)(void),
898 void (*board_reset)(void),
899 void (*board_de_reset)(void))
900{
901 fsl_ddr_info_t info;
902
903
904 memset(&info, 0, sizeof(fsl_ddr_info_t));
905 info.mem_base = base;
906 info.first_ctrl = first_ctrl;
907 info.num_ctrls = num_ctrls;
908 info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
909 info.board_need_mem_reset = board_need_reset;
910 info.board_mem_reset = board_reset;
911 info.board_mem_de_reset = board_de_reset;
912
913 return __fsl_ddr_sdram(&info);
914}
915#endif
916
917
918
919
920
921phys_size_t
922fsl_ddr_sdram_size(void)
923{
924 fsl_ddr_info_t info;
925 unsigned long long total_memory = 0;
926
927 memset(&info, 0 , sizeof(fsl_ddr_info_t));
928 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
929 info.first_ctrl = 0;
930 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
931 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
932 info.board_need_mem_reset = NULL;
933 remove_unused_controllers(&info);
934
935
936 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
937
938 return total_memory;
939}
940