LXR uboot/drivers/mmc/bcmstb

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2018  Cisco Systems, Inc.
   4 * (C) Copyright 2019  Synamedia
   5 *
   6 * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
   7 */
   8
   9#include <common.h>
  10#include <dm.h>
  11#include <mach/sdhci.h>
  12#include <malloc.h>
  13#include <sdhci.h>
  14
  15/*
  16 * The BCMSTB SDHCI has a quirk in that its actual maximum frequency
  17 * capability is 100 MHz.  The divisor that is eventually written to
  18 * SDHCI_CLOCK_CONTROL is calculated based on what the MMC device
  19 * reports, and relative to this maximum frequency.
  20 *
  21 * This define used to be set to 52000000 (52 MHz), the desired
  22 * maximum frequency, but that would result in the communication
  23 * actually running at 100 MHz (seemingly without issue), which is
  24 * out-of-spec.
  25 *
  26 * Now, by setting this to 0 (auto-detect), 100 MHz will be read from
  27 * the capabilities register, and the resulting divisor will be
  28 * doubled, meaning that the clock control register will be set to the
  29 * in-spec 52 MHz value.
  30 */
  31#define BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY    0
  32/*
  33 * When the minimum clock frequency is set to 0 (auto-detect), U-Boot
  34 * sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
  35 * which results in the controller timing out when trying to
  36 * communicate with the MMC device.  Hard-code this value to 400000
  37 * (400 kHz) to prevent this.
  38 */
  39#define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY    400000
  40
  41/*
  42 * This driver has only been tested with eMMC devices; SD devices may
  43 * not work.
  44 */
  45struct sdhci_bcmstb_plat {
  46        struct mmc_config cfg;
  47        struct mmc mmc;
  48};
  49
  50static int sdhci_bcmstb_bind(struct udevice *dev)
  51{
  52        struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
  53
  54        return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  55}
  56
  57static int sdhci_bcmstb_probe(struct udevice *dev)
  58{
  59        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  60        struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
  61        struct sdhci_host *host = dev_get_priv(dev);
  62        fdt_addr_t base;
  63        int ret;
  64
  65        base = dev_read_addr(dev);
  66        if (base == FDT_ADDR_T_NONE)
  67                return -EINVAL;
  68
  69        host->name = dev->name;
  70        host->ioaddr = (void *)base;
  71
  72        ret = mmc_of_parse(dev, &plat->cfg);
  73        if (ret)
  74                return ret;
  75
  76        host->mmc = &plat->mmc;
  77        host->mmc->dev = dev;
  78        ret = sdhci_setup_cfg(&plat->cfg, host,
  79                              BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
  80                              BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
  81        if (ret)
  82                return ret;
  83
  84        upriv->mmc = &plat->mmc;
  85        host->mmc->priv = host;
  86
  87        return sdhci_probe(dev);
  88}
  89
  90static const struct udevice_id sdhci_bcmstb_match[] = {
  91        { .compatible = "brcm,bcm7425-sdhci" },
  92        { .compatible = "brcm,sdhci-brcmstb" },
  93        { }
  94};
  95
  96U_BOOT_DRIVER(sdhci_bcmstb) = {
  97        .name = "sdhci-bcmstb",
  98        .id = UCLASS_MMC,
  99        .of_match = sdhci_bcmstb_match,
 100        .ops = &sdhci_ops,
 101        .bind = sdhci_bcmstb_bind,
 102        .probe = sdhci_bcmstb_probe,
 103        .priv_auto_alloc_size = sizeof(struct sdhci_host),
 104        .platdata_auto_alloc_size = sizeof(struct sdhci_bcmstb_plat),
 105};
 106