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8#include <config.h>
9#include <common.h>
10#include <cpu_func.h>
11#include <dm.h>
12#include <log.h>
13#include <net.h>
14#include <malloc.h>
15#include <asm/io.h>
16#include <phy.h>
17#include <miiphy.h>
18#include <wait_bit.h>
19#include <linux/delay.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23
24#define XAE_EMMC_LINKSPEED_MASK 0xC0000000
25#define XAE_EMMC_LINKSPD_10 0x00000000
26#define XAE_EMMC_LINKSPD_100 0x40000000
27#define XAE_EMMC_LINKSPD_1000 0x80000000
28
29
30#define XAE_INT_RXRJECT_MASK 0x00000008
31#define XAE_INT_MGTRDY_MASK 0x00000080
32
33
34#define XAE_RCW1_RX_MASK 0x10000000
35
36
37#define XAE_TC_TX_MASK 0x10000000
38
39#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
40
41
42#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040
43
44
45#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000
46#define XAE_MDIO_MCR_PHYAD_SHIFT 24
47#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000
48#define XAE_MDIO_MCR_REGAD_SHIFT 16
49#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000
50#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000
51#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800
52#define XAE_MDIO_MCR_READY_MASK 0x00000080
53
54#define XAE_MDIO_DIV_DFT 29
55
56#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF
57
58
59
60#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001
61#define XAXIDMA_CR_RESET_MASK 0x00000004
62
63
64#define XAXIDMA_HALTED_MASK 0x00000001
65
66
67#define XAXIDMA_IRQ_IOC_MASK 0x00001000
68#define XAXIDMA_IRQ_DELAY_MASK 0x00002000
69#define XAXIDMA_IRQ_ALL_MASK 0x00007000
70
71
72#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000
73#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000
74
75#define DMAALIGN 128
76
77static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
78
79
80struct axidma_reg {
81 u32 control;
82 u32 status;
83 u32 current;
84 u32 current_hi;
85 u32 tail;
86 u32 tail_hi;
87};
88
89
90struct axidma_priv {
91 struct axidma_reg *dmatx;
92 struct axidma_reg *dmarx;
93 int phyaddr;
94 struct axi_regs *iobase;
95 phy_interface_t interface;
96 struct phy_device *phydev;
97 struct mii_dev *bus;
98 u8 eth_hasnobuf;
99 int phy_of_handle;
100};
101
102
103struct axidma_bd {
104 u32 next_desc;
105 u32 next_desc_msb;
106 u32 buf_addr;
107 u32 buf_addr_msb;
108 u32 reserved3;
109 u32 reserved4;
110 u32 cntrl;
111 u32 status;
112 u32 app0;
113 u32 app1;
114 u32 app2;
115 u32 app3;
116 u32 app4;
117 u32 sw_id_offset;
118 u32 reserved5;
119 u32 reserved6;
120};
121
122
123static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
124static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
125
126struct axi_regs {
127 u32 reserved[3];
128 u32 is;
129 u32 reserved2;
130 u32 ie;
131 u32 reserved3[251];
132 u32 rcw1;
133 u32 tc;
134 u32 reserved4;
135 u32 emmc;
136 u32 reserved5[59];
137 u32 mdio_mc;
138 u32 mdio_mcr;
139 u32 mdio_mwd;
140 u32 mdio_mrd;
141 u32 reserved6[124];
142 u32 uaw0;
143 u32 uaw1;
144};
145
146
147#define PHY_DETECT_REG 1
148
149
150
151
152
153
154
155
156#define PHY_DETECT_MASK 0x1808
157
158static inline int mdio_wait(struct axi_regs *regs)
159{
160 u32 timeout = 200;
161
162
163 while (timeout && (!(readl(®s->mdio_mcr)
164 & XAE_MDIO_MCR_READY_MASK))) {
165 timeout--;
166 udelay(1);
167 }
168 if (!timeout) {
169 printf("%s: Timeout\n", __func__);
170 return 1;
171 }
172 return 0;
173}
174
175
176
177
178
179
180
181
182static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
183{
184#if defined(CONFIG_PHYS_64BIT)
185 writeq((unsigned long)bd, desc);
186#else
187 writel((u32)bd, desc);
188#endif
189}
190
191static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
192 u16 *val)
193{
194 struct axi_regs *regs = priv->iobase;
195 u32 mdioctrlreg = 0;
196
197 if (mdio_wait(regs))
198 return 1;
199
200 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
201 XAE_MDIO_MCR_PHYAD_MASK) |
202 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
203 & XAE_MDIO_MCR_REGAD_MASK) |
204 XAE_MDIO_MCR_INITIATE_MASK |
205 XAE_MDIO_MCR_OP_READ_MASK;
206
207 writel(mdioctrlreg, ®s->mdio_mcr);
208
209 if (mdio_wait(regs))
210 return 1;
211
212
213 *val = readl(®s->mdio_mrd);
214 return 0;
215}
216
217static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
218 u32 data)
219{
220 struct axi_regs *regs = priv->iobase;
221 u32 mdioctrlreg = 0;
222
223 if (mdio_wait(regs))
224 return 1;
225
226 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
227 XAE_MDIO_MCR_PHYAD_MASK) |
228 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
229 & XAE_MDIO_MCR_REGAD_MASK) |
230 XAE_MDIO_MCR_INITIATE_MASK |
231 XAE_MDIO_MCR_OP_WRITE_MASK;
232
233
234 writel(data, ®s->mdio_mwd);
235
236 writel(mdioctrlreg, ®s->mdio_mcr);
237
238 if (mdio_wait(regs))
239 return 1;
240
241 return 0;
242}
243
244static int axiemac_phy_init(struct udevice *dev)
245{
246 u16 phyreg;
247 int i;
248 u32 ret;
249 struct axidma_priv *priv = dev_get_priv(dev);
250 struct axi_regs *regs = priv->iobase;
251 struct phy_device *phydev;
252
253 u32 supported = SUPPORTED_10baseT_Half |
254 SUPPORTED_10baseT_Full |
255 SUPPORTED_100baseT_Half |
256 SUPPORTED_100baseT_Full |
257 SUPPORTED_1000baseT_Half |
258 SUPPORTED_1000baseT_Full;
259
260
261 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
262
263 if (priv->phyaddr == -1) {
264
265 for (i = 31; i >= 0; i--) {
266 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
267 if (!ret && (phyreg != 0xFFFF) &&
268 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
269
270 priv->phyaddr = i;
271 debug("axiemac: Found valid phy address, %x\n",
272 i);
273 break;
274 }
275 }
276 }
277
278
279 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
280
281 phydev->supported &= supported;
282 phydev->advertising = phydev->supported;
283 priv->phydev = phydev;
284 if (priv->phy_of_handle)
285 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
286 phy_config(phydev);
287
288 return 0;
289}
290
291
292static int setup_phy(struct udevice *dev)
293{
294 u16 temp;
295 u32 speed, emmc_reg, ret;
296 struct axidma_priv *priv = dev_get_priv(dev);
297 struct axi_regs *regs = priv->iobase;
298 struct phy_device *phydev = priv->phydev;
299
300 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
301
302
303
304
305
306 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
307 if (ret)
308 return 0;
309 if (temp & BMCR_ISOLATE) {
310 temp &= ~BMCR_ISOLATE;
311 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
312 if (ret)
313 return 0;
314 }
315 }
316
317 if (phy_startup(phydev)) {
318 printf("axiemac: could not initialize PHY %s\n",
319 phydev->dev->name);
320 return 0;
321 }
322 if (!phydev->link) {
323 printf("%s: No link.\n", phydev->dev->name);
324 return 0;
325 }
326
327 switch (phydev->speed) {
328 case 1000:
329 speed = XAE_EMMC_LINKSPD_1000;
330 break;
331 case 100:
332 speed = XAE_EMMC_LINKSPD_100;
333 break;
334 case 10:
335 speed = XAE_EMMC_LINKSPD_10;
336 break;
337 default:
338 return 0;
339 }
340
341
342 emmc_reg = readl(®s->emmc);
343 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
344 emmc_reg |= speed;
345
346
347 writel(emmc_reg, ®s->emmc);
348
349
350
351
352
353
354 udelay(1);
355
356 return 1;
357}
358
359
360static void axiemac_stop(struct udevice *dev)
361{
362 struct axidma_priv *priv = dev_get_priv(dev);
363 u32 temp;
364
365
366 temp = readl(&priv->dmatx->control);
367 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
368 writel(temp, &priv->dmatx->control);
369
370 temp = readl(&priv->dmarx->control);
371 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
372 writel(temp, &priv->dmarx->control);
373
374 debug("axiemac: Halted\n");
375}
376
377static int axi_ethernet_init(struct axidma_priv *priv)
378{
379 struct axi_regs *regs = priv->iobase;
380 int err;
381
382
383
384
385
386
387
388
389
390
391 if (!priv->eth_hasnobuf) {
392 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
393 true, 200, false);
394 if (err) {
395 printf("%s: Timeout\n", __func__);
396 return 1;
397 }
398
399
400
401
402
403 writel(0, ®s->ie);
404 }
405
406
407 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
408
409
410
411
412
413 if (!priv->eth_hasnobuf) {
414
415 writel(XAE_INT_RXRJECT_MASK, ®s->is);
416 }
417
418
419
420 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
421
422 debug("axiemac: InitHw done\n");
423 return 0;
424}
425
426static int axiemac_write_hwaddr(struct udevice *dev)
427{
428 struct eth_pdata *pdata = dev_get_platdata(dev);
429 struct axidma_priv *priv = dev_get_priv(dev);
430 struct axi_regs *regs = priv->iobase;
431
432
433 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
434 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
435 writel(val, ®s->uaw0);
436
437 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
438 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
439 writel(val, ®s->uaw1);
440 return 0;
441}
442
443
444static void axi_dma_init(struct axidma_priv *priv)
445{
446 u32 timeout = 500;
447
448
449 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
450 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
451
452
453 while (timeout--) {
454
455
456 if (!((readl(&priv->dmatx->control) |
457 readl(&priv->dmarx->control))
458 & XAXIDMA_CR_RESET_MASK)) {
459 break;
460 }
461 }
462 if (!timeout)
463 printf("%s: Timeout\n", __func__);
464}
465
466static int axiemac_start(struct udevice *dev)
467{
468 struct axidma_priv *priv = dev_get_priv(dev);
469 struct axi_regs *regs = priv->iobase;
470 u32 temp;
471
472 debug("axiemac: Init started\n");
473
474
475
476
477
478
479 axi_dma_init(priv);
480
481
482 if (axi_ethernet_init(priv))
483 return -1;
484
485
486 temp = readl(&priv->dmarx->control);
487 temp &= ~XAXIDMA_IRQ_ALL_MASK;
488 writel(temp, &priv->dmarx->control);
489
490
491 axienet_dma_write(&rx_bd, &priv->dmarx->current);
492
493
494 memset(&rx_bd, 0, sizeof(rx_bd));
495 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
496 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
497#if defined(CONFIG_PHYS_64BIT)
498 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
499 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
500#endif
501 rx_bd.cntrl = sizeof(rxframe);
502
503 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
504
505
506
507 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
508
509
510 temp = readl(&priv->dmarx->control);
511 temp |= XAXIDMA_CR_RUNSTOP_MASK;
512 writel(temp, &priv->dmarx->control);
513
514
515 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
516
517
518 writel(XAE_TC_TX_MASK, ®s->tc);
519
520 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
521
522
523 if (!setup_phy(dev)) {
524 axiemac_stop(dev);
525 return -1;
526 }
527
528 debug("axiemac: Init complete\n");
529 return 0;
530}
531
532static int axiemac_send(struct udevice *dev, void *ptr, int len)
533{
534 struct axidma_priv *priv = dev_get_priv(dev);
535 u32 timeout;
536
537 if (len > PKTSIZE_ALIGN)
538 len = PKTSIZE_ALIGN;
539
540
541 flush_cache((phys_addr_t)ptr, len);
542
543
544 memset(&tx_bd, 0, sizeof(tx_bd));
545
546 tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
547 tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
548#if defined(CONFIG_PHYS_64BIT)
549 tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
550 tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
551#endif
552
553 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
554 XAXIDMA_BD_CTRL_TXEOF_MASK;
555
556
557 flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
558
559 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
560 u32 temp;
561 axienet_dma_write(&tx_bd, &priv->dmatx->current);
562
563 temp = readl(&priv->dmatx->control);
564 temp |= XAXIDMA_CR_RUNSTOP_MASK;
565 writel(temp, &priv->dmatx->control);
566 }
567
568
569 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
570
571
572 debug("axiemac: Waiting for tx to be done\n");
573 timeout = 200;
574 while (timeout && (!(readl(&priv->dmatx->status) &
575 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
576 timeout--;
577 udelay(1);
578 }
579 if (!timeout) {
580 printf("%s: Timeout\n", __func__);
581 return 1;
582 }
583
584 debug("axiemac: Sending complete\n");
585 return 0;
586}
587
588static int isrxready(struct axidma_priv *priv)
589{
590 u32 status;
591
592
593 status = readl(&priv->dmarx->status);
594
595
596 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
597
598
599
600
601
602 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
603 return 1;
604
605 return 0;
606}
607
608static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
609{
610 u32 length;
611 struct axidma_priv *priv = dev_get_priv(dev);
612 u32 temp;
613
614
615 if (!isrxready(priv))
616 return -1;
617
618 debug("axiemac: RX data ready\n");
619
620
621 temp = readl(&priv->dmarx->control);
622 temp &= ~XAXIDMA_IRQ_ALL_MASK;
623 writel(temp, &priv->dmarx->control);
624 if (!priv->eth_hasnobuf)
625 length = rx_bd.app4 & 0xFFFF;
626 else
627 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
628
629#ifdef DEBUG
630 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
631#endif
632
633 *packetp = rxframe;
634 return length;
635}
636
637static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
638{
639 struct axidma_priv *priv = dev_get_priv(dev);
640
641#ifdef DEBUG
642
643 memset(rxframe, 0, sizeof(rxframe));
644#endif
645
646
647 memset(&rx_bd, 0, sizeof(rx_bd));
648 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
649 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
650#if defined(CONFIG_PHYS_64BIT)
651 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
652 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
653#endif
654 rx_bd.cntrl = sizeof(rxframe);
655
656
657 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
658
659
660
661 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
662
663
664 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
665
666 debug("axiemac: RX completed, framelength = %d\n", length);
667
668 return 0;
669}
670
671static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
672 int devad, int reg)
673{
674 int ret;
675 u16 value;
676
677 ret = phyread(bus->priv, addr, reg, &value);
678 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
679 value, ret);
680 return value;
681}
682
683static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
684 int reg, u16 value)
685{
686 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
687 return phywrite(bus->priv, addr, reg, value);
688}
689
690static int axi_emac_probe(struct udevice *dev)
691{
692 struct axidma_priv *priv = dev_get_priv(dev);
693 int ret;
694
695 priv->bus = mdio_alloc();
696 priv->bus->read = axiemac_miiphy_read;
697 priv->bus->write = axiemac_miiphy_write;
698 priv->bus->priv = priv;
699
700 ret = mdio_register_seq(priv->bus, dev->seq);
701 if (ret)
702 return ret;
703
704 axiemac_phy_init(dev);
705
706 return 0;
707}
708
709static int axi_emac_remove(struct udevice *dev)
710{
711 struct axidma_priv *priv = dev_get_priv(dev);
712
713 free(priv->phydev);
714 mdio_unregister(priv->bus);
715 mdio_free(priv->bus);
716
717 return 0;
718}
719
720static const struct eth_ops axi_emac_ops = {
721 .start = axiemac_start,
722 .send = axiemac_send,
723 .recv = axiemac_recv,
724 .free_pkt = axiemac_free_pkt,
725 .stop = axiemac_stop,
726 .write_hwaddr = axiemac_write_hwaddr,
727};
728
729static int axi_emac_ofdata_to_platdata(struct udevice *dev)
730{
731 struct eth_pdata *pdata = dev_get_platdata(dev);
732 struct axidma_priv *priv = dev_get_priv(dev);
733 int node = dev_of_offset(dev);
734 int offset = 0;
735 const char *phy_mode;
736
737 pdata->iobase = dev_read_addr(dev);
738 priv->iobase = (struct axi_regs *)pdata->iobase;
739
740 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
741 "axistream-connected");
742 if (offset <= 0) {
743 printf("%s: axistream is not found\n", __func__);
744 return -EINVAL;
745 }
746 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
747 offset, "reg");
748 if (!priv->dmatx) {
749 printf("%s: axi_dma register space not found\n", __func__);
750 return -EINVAL;
751 }
752
753 priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
754
755 priv->phyaddr = -1;
756
757 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
758 if (offset > 0) {
759 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
760 priv->phy_of_handle = offset;
761 }
762
763 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
764 if (phy_mode)
765 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
766 if (pdata->phy_interface == -1) {
767 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
768 return -EINVAL;
769 }
770 priv->interface = pdata->phy_interface;
771
772 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
773 "xlnx,eth-hasnobuf");
774
775 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
776 priv->phyaddr, phy_string_for_interface(priv->interface));
777
778 return 0;
779}
780
781static const struct udevice_id axi_emac_ids[] = {
782 { .compatible = "xlnx,axi-ethernet-1.00.a" },
783 { }
784};
785
786U_BOOT_DRIVER(axi_emac) = {
787 .name = "axi_emac",
788 .id = UCLASS_ETH,
789 .of_match = axi_emac_ids,
790 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
791 .probe = axi_emac_probe,
792 .remove = axi_emac_remove,
793 .ops = &axi_emac_ops,
794 .priv_auto_alloc_size = sizeof(struct axidma_priv),
795 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
796};
797