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4
5
6#include <common.h>
7#include <env.h>
8#include <init.h>
9#include <log.h>
10#include <malloc.h>
11#include <asm/fsl_serdes.h>
12#include <linux/delay.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
16
17
18
19
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27
28
29
30#include <pci.h>
31#include <asm/io.h>
32#include <asm/fsl_pci.h>
33
34#ifndef CONFIG_SYS_PCI_MEMORY_BUS
35#define CONFIG_SYS_PCI_MEMORY_BUS 0
36#endif
37
38#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
39#define CONFIG_SYS_PCI_MEMORY_PHYS 0
40#endif
41
42#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
43#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
44#endif
45
46
47
48
49
50static void set_inbound_window(volatile pit_t *pi,
51 struct pci_region *r,
52 u64 size)
53{
54 u32 sz = (__ilog2_u64(size) - 1);
55#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
56 u32 flag = 0;
57#else
58 u32 flag = PIWAR_LOCAL;
59#endif
60
61 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
62
63 out_be32(&pi->pitar, r->phys_start >> 12);
64 out_be32(&pi->piwbar, r->bus_start >> 12);
65#ifdef CONFIG_SYS_PCI_64BIT
66 out_be32(&pi->piwbear, r->bus_start >> 44);
67#else
68 out_be32(&pi->piwbear, 0);
69#endif
70 if (r->flags & PCI_REGION_PREFETCH)
71 flag |= PIWAR_PF;
72 out_be32(&pi->piwar, flag | sz);
73}
74
75int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
76{
77 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
78
79
80 memset(hose, 0, sizeof(struct pci_controller));
81
82 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
83
84 return fsl_is_pci_agent(hose);
85}
86
87static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
88 u64 out_lo, u8 pcie_cap,
89 volatile pit_t *pi)
90{
91 struct pci_region *r = hose->regions + hose->region_count;
92 u64 sz = min((u64)gd->ram_size, (1ull << 32));
93
94 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
95 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
96 pci_size_t pci_sz;
97
98
99 if (bus_start > out_lo) {
100 printf ("no space for inbound mapping of memory\n");
101 return 0;
102 }
103
104
105 if ((bus_start + sz) > out_lo) {
106 sz = out_lo - bus_start;
107 debug ("limiting size to %llx\n", sz);
108 }
109
110 pci_sz = 1ull << __ilog2_u64(sz);
111
112
113
114
115 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
116 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
117 (u64)bus_start, (u64)phys_start, (u64)sz);
118 pci_set_region(r, bus_start, phys_start, sz,
119 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
120 PCI_REGION_PREFETCH);
121
122
123
124
125
126 if (pci_sz != sz)
127 sz = 2ull << __ilog2_u64(sz);
128
129 set_inbound_window(pi--, r++, sz);
130 sz = 0;
131 } else {
132 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
133 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
134 pci_set_region(r, bus_start, phys_start, pci_sz,
135 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
136 PCI_REGION_PREFETCH);
137 set_inbound_window(pi--, r++, pci_sz);
138
139 sz -= pci_sz;
140 bus_start += pci_sz;
141 phys_start += pci_sz;
142
143 pci_sz = 1ull << __ilog2_u64(sz);
144 if (sz) {
145 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
146 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
147 pci_set_region(r, bus_start, phys_start, pci_sz,
148 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
149 PCI_REGION_PREFETCH);
150 set_inbound_window(pi--, r++, pci_sz);
151 sz -= pci_sz;
152 bus_start += pci_sz;
153 phys_start += pci_sz;
154 }
155 }
156
157#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
158
159
160
161
162 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
163
164 if (gd->ram_size > pci_sz)
165 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
166 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
167 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
168 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
169 (u64)pci_sz);
170 pci_set_region(r,
171 CONFIG_SYS_PCI64_MEMORY_BUS,
172 CONFIG_SYS_PCI_MEMORY_PHYS,
173 pci_sz,
174 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
175 PCI_REGION_PREFETCH);
176 set_inbound_window(pi--, r++, pci_sz);
177#else
178 pci_sz = 1ull << __ilog2_u64(sz);
179 if (sz) {
180 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
181 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
182 pci_set_region(r, bus_start, phys_start, pci_sz,
183 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
184 PCI_REGION_PREFETCH);
185 sz -= pci_sz;
186 bus_start += pci_sz;
187 phys_start += pci_sz;
188 set_inbound_window(pi--, r++, pci_sz);
189 }
190#endif
191
192#ifdef CONFIG_PHYS_64BIT
193 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
194 printf("Was not able to map all of memory via "
195 "inbound windows -- %lld remaining\n", sz);
196#endif
197
198 hose->region_count = r - hose->regions;
199
200 return 1;
201}
202
203#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
204static void fsl_pcie_boot_master(pit_t *pi)
205{
206
207 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
208 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
209 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
210 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
211 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
212 struct pci_region r_inbound;
213 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
214 - 1;
215 pci_set_region(&r_inbound,
216 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
217 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
218 sz_inbound,
219 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
220
221 set_inbound_window(pi--, &r_inbound,
222 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
223
224
225 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
226 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
227 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
228 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
229 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
230 pci_set_region(&r_inbound,
231 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
232 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
233 sz_inbound,
234 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
235
236 set_inbound_window(pi--, &r_inbound,
237 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
238
239
240 debug("PCIEBOOT - MASTER: Inbound window for slave's "
241 "ucode and ENV; "
242 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
243 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
244 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
245 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
246 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
247 - 1;
248 pci_set_region(&r_inbound,
249 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
250 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
251 sz_inbound,
252 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
253
254 set_inbound_window(pi--, &r_inbound,
255 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
256}
257
258static void fsl_pcie_boot_master_release_slave(int port)
259{
260 unsigned long release_addr;
261
262
263 switch (port) {
264 case 1:
265 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
266 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
267 break;
268#ifdef CONFIG_SYS_PCIE2_MEM_VIRT
269 case 2:
270 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
271 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
272 break;
273#endif
274#ifdef CONFIG_SYS_PCIE3_MEM_VIRT
275 case 3:
276 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
277 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
278 break;
279#endif
280 default:
281 release_addr = 0;
282 break;
283 }
284 if (release_addr != 0) {
285 out_be32((void *)release_addr,
286 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
287 debug("PCIEBOOT - MASTER: "
288 "Release slave successfully! Now the slave should start up!\n");
289 } else {
290 debug("PCIEBOOT - MASTER: "
291 "Release slave failed!\n");
292 }
293}
294#endif
295
296void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
297{
298 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
299 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
300 u16 temp16;
301 u32 temp32;
302 u32 block_rev;
303 int enabled, r, inbound = 0;
304 u16 ltssm;
305 u8 temp8, pcie_cap;
306 int pcie_cap_pos;
307 int pci_dcr;
308 int pci_dsr;
309 int pci_lsr;
310
311#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
312 int pci_lcr;
313#endif
314
315 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
316 struct pci_region *reg = hose->regions + hose->region_count;
317 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
318
319
320 volatile pot_t *po = &pci->pot[1];
321 volatile pit_t *pi;
322
323 u64 out_hi = 0, out_lo = -1ULL;
324 u32 pcicsrbar, pcicsrbar_sz;
325
326 pci_setup_indirect(hose, cfg_addr, cfg_data);
327
328#ifdef PEX_CCB_DIV
329
330 pci_hose_write_config_dword(hose, dev, 0x440,
331 ((gd->bus_clk / 1000000) *
332 (16 / PEX_CCB_DIV)) / 333);
333#endif
334 block_rev = in_be32(&pci->block_rev1);
335 if (PEX_IP_BLK_REV_2_2 <= block_rev) {
336 pi = &pci->pit[2];
337 } else {
338 pi = &pci->pit[3];
339 }
340
341
342 for (r = 0; r < hose->region_count; r++) {
343 unsigned long flags = hose->regions[r].flags;
344 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
345
346 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
347 if (flags != PCI_REGION_SYS_MEMORY) {
348 u64 start = hose->regions[r].bus_start;
349 u64 end = start + hose->regions[r].size;
350
351 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
352 out_be32(&po->potar, start >> 12);
353#ifdef CONFIG_SYS_PCI_64BIT
354 out_be32(&po->potear, start >> 44);
355#else
356 out_be32(&po->potear, 0);
357#endif
358 if (hose->regions[r].flags & PCI_REGION_IO) {
359 out_be32(&po->powar, POWAR_EN | sz |
360 POWAR_IO_READ | POWAR_IO_WRITE);
361 } else {
362 out_be32(&po->powar, POWAR_EN | sz |
363 POWAR_MEM_READ | POWAR_MEM_WRITE);
364 out_lo = min(start, out_lo);
365 out_hi = max(end, out_hi);
366 }
367 po++;
368 }
369 }
370 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
371
372
373 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
374 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
375 pcicsrbar_sz = ~pcicsrbar_sz + 1;
376
377 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
378 (out_lo > 0x100000000ull))
379 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
380 else
381 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
382 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
383
384 out_lo = min(out_lo, (u64)pcicsrbar);
385
386 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
387
388 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
389 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
390 hose->region_count++;
391
392
393 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
394 pci_dcr = pcie_cap_pos + 0x08;
395 pci_dsr = pcie_cap_pos + 0x0a;
396 pci_lsr = pcie_cap_pos + 0x12;
397
398 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
399
400#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
401
402 char *s = env_get("bootmaster");
403 char pcie[6];
404 sprintf(pcie, "PCIE%d", pci_info->pci_num);
405
406 if (s && (strcmp(s, pcie) == 0)) {
407 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
408 pci_info->pci_num);
409 fsl_pcie_boot_master((pit_t *)pi);
410 } else {
411
412 inbound = fsl_pci_setup_inbound_windows(hose,
413 out_lo, pcie_cap, pi);
414 }
415#else
416
417 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
418#endif
419
420 for (r = 0; r < hose->region_count; r++)
421 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
422 (u64)hose->regions[r].phys_start,
423 (u64)hose->regions[r].bus_start,
424 (u64)hose->regions[r].size,
425 hose->regions[r].flags);
426
427 pci_register_hose(hose);
428 pciauto_config_init(hose);
429 hose->current_busno = hose->first_busno;
430
431 out_be32(&pci->pedr, 0xffffffff);
432 out_be32(&pci->peer, ~0x20140);
433
434
435
436
437 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
438 temp32 |= 0xf000e;
439 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
440
441#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
442 pci_lcr = pcie_cap_pos + 0x10;
443 temp32 = 0;
444 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
445 temp32 &= ~0x03;
446 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
447 udelay(1);
448#endif
449 if (pcie_cap == PCI_CAP_ID_EXP) {
450 if (block_rev >= PEX_IP_BLK_REV_3_0) {
451#define PEX_CSR0_LTSSM_MASK 0xFC
452#define PEX_CSR0_LTSSM_SHIFT 2
453 ltssm = (in_be32(&pci->pex_csr0)
454 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
455 enabled = (ltssm == 0x11) ? 1 : 0;
456#ifdef CONFIG_FSL_PCIE_RESET
457 int i;
458
459 setbits_be32(&pci->pdb_stat, 0x08000000);
460 (void) in_be32(&pci->pdb_stat);
461 udelay(1000);
462
463 clrbits_be32(&pci->pdb_stat, 0x08000000);
464 asm("sync;isync");
465 for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
466 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
467 <ssm);
468 udelay(1000);
469 }
470#endif
471 } else {
472
473
474 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
475 enabled = ltssm >= PCI_LTSSM_L0;
476
477#ifdef CONFIG_FSL_PCIE_RESET
478 if (ltssm == 1) {
479 int i;
480 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
481
482 setbits_be32(&pci->pdb_stat, 0x08000000);
483 (void) in_be32(&pci->pdb_stat);
484 udelay(100);
485 debug(" Asserting PCIe reset @%p = %x\n",
486 &pci->pdb_stat, in_be32(&pci->pdb_stat));
487
488 clrbits_be32(&pci->pdb_stat, 0x08000000);
489 asm("sync;isync");
490 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
491 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
492 <ssm);
493 udelay(1000);
494 debug("....PCIe link error. "
495 "LTSSM=0x%02x.\n", ltssm);
496 }
497 enabled = ltssm >= PCI_LTSSM_L0;
498
499
500
501
502 pci_hose_write_config_dword(hose, dev,
503 PCI_BASE_ADDRESS_0, pcicsrbar);
504 }
505#endif
506 }
507
508#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
509 if (enabled == 0) {
510 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
511 temp32 = in_be32(&srds_regs->srdspccr0);
512
513 if ((temp32 >> 28) == 3) {
514 int i;
515
516 out_be32(&srds_regs->srdspccr0, 2 << 28);
517 setbits_be32(&pci->pdb_stat, 0x08000000);
518 in_be32(&pci->pdb_stat);
519 udelay(100);
520 clrbits_be32(&pci->pdb_stat, 0x08000000);
521 asm("sync;isync");
522 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
523 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
524 udelay(1000);
525 }
526 enabled = ltssm >= PCI_LTSSM_L0;
527 }
528 }
529#endif
530 if (!enabled) {
531
532
533
534
535 if (fsl_is_pci_agent(hose))
536 printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
537 else
538 printf("no link, regs @ 0x%lx\n", pci_info->regs);
539 hose->last_busno = hose->first_busno;
540 return;
541 }
542
543 out_be32(&pci->pme_msg_det, 0xffffffff);
544 out_be32(&pci->pme_msg_int_en, 0xffffffff);
545
546
547 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
548 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
549 (temp16 & 0xf), pci_info->regs);
550
551 hose->current_busno++;
552 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
553 }
554
555#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
556
557
558
559 clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
560#endif
561
562
563
564
565
566 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
567 hose->pci_prefetch, hose->pci_io);
568
569 if (inbound) {
570 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
571 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
572 temp16 | PCI_COMMAND_MEMORY);
573 }
574
575#ifndef CONFIG_PCI_NOSCAN
576 if (!fsl_is_pci_agent(hose)) {
577 debug(" Scanning PCI bus %02x\n",
578 hose->current_busno);
579 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
580 } else {
581 debug(" Not scanning PCI bus %02x. PI=%x\n",
582 hose->current_busno, temp8);
583 hose->last_busno = hose->current_busno;
584 }
585
586
587
588
589 if (pcie_cap == PCI_CAP_ID_EXP) {
590 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
591 }
592#else
593 hose->last_busno = hose->current_busno;
594#endif
595
596
597 if (pcie_cap == PCI_CAP_ID_EXP)
598 out_be32(&pci->pme_msg_det, 0xffffffff);
599 out_be32(&pci->pedr, 0xffffffff);
600
601 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
602 if (temp16) {
603 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
604 }
605
606 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
607 if (temp16) {
608 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
609 }
610}
611
612int fsl_is_pci_agent(struct pci_controller *hose)
613{
614 int pcie_cap_pos;
615 u8 pcie_cap;
616 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
617
618 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
619 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
620 if (pcie_cap == PCI_CAP_ID_EXP) {
621 u8 header_type;
622
623 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
624 &header_type);
625 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
626 } else {
627 u8 prog_if;
628
629 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
630
631
632
633
634 return (prog_if == FSL_PROG_IF_AGENT);
635 }
636}
637
638int fsl_pci_init_port(struct fsl_pci_info *pci_info,
639 struct pci_controller *hose, int busno)
640{
641 volatile ccsr_fsl_pci_t *pci;
642 struct pci_region *r;
643 pci_dev_t dev = PCI_BDF(busno,0,0);
644 int pcie_cap_pos;
645 u8 pcie_cap;
646
647 pci = (ccsr_fsl_pci_t *) pci_info->regs;
648
649
650
651
652 if (in_be32(&pci->pme_msg_det)) {
653 out_be32(&pci->pme_msg_det, 0xffffffff);
654 debug (" with errors. Clearing. Now 0x%08x",
655 pci->pme_msg_det);
656 }
657
658 r = hose->regions + hose->region_count;
659
660
661 pci_set_region(r++,
662 pci_info->mem_bus,
663 pci_info->mem_phys,
664 pci_info->mem_size,
665 PCI_REGION_MEM);
666
667
668 pci_set_region(r++,
669 pci_info->io_bus,
670 pci_info->io_phys,
671 pci_info->io_size,
672 PCI_REGION_IO);
673
674 hose->region_count = r - hose->regions;
675 hose->first_busno = busno;
676
677 fsl_pci_init(hose, pci_info);
678
679 if (fsl_is_pci_agent(hose)) {
680 fsl_pci_config_unlock(hose);
681 hose->last_busno = hose->first_busno;
682#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
683 } else {
684
685 char *s = env_get("bootmaster");
686 char pcie[6];
687 sprintf(pcie, "PCIE%d", pci_info->pci_num);
688
689 if (s && (strcmp(s, pcie) == 0))
690 fsl_pcie_boot_master_release_slave(pci_info->pci_num);
691#endif
692 }
693
694 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
695 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
696 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
697 "e" : "", pci_info->pci_num,
698 hose->first_busno, hose->last_busno);
699 return(hose->last_busno + 1);
700}
701
702
703void fsl_pci_config_unlock(struct pci_controller *hose)
704{
705 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
706 int pcie_cap_pos;
707 u8 pcie_cap;
708 u16 pbfr;
709
710 if (!fsl_is_pci_agent(hose))
711 return;
712
713 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
714 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
715 if (pcie_cap != 0x0) {
716 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
717 u32 block_rev = in_be32(&pci->block_rev1);
718
719 if (block_rev >= PEX_IP_BLK_REV_3_0)
720 setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
721 else
722 pci_hose_write_config_byte(hose, dev,
723 FSL_PCIE_CFG_RDY, 0x1);
724 } else {
725
726 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
727 pbfr &= ~0x20;
728 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
729 }
730}
731
732#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
733 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
734int fsl_configure_pcie(struct fsl_pci_info *info,
735 struct pci_controller *hose,
736 const char *connected, int busno)
737{
738 int is_endpoint;
739
740 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
741 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
742
743 is_endpoint = fsl_setup_hose(hose, info->regs);
744 printf("PCIe%u: %s", info->pci_num,
745 is_endpoint ? "Endpoint" : "Root Complex");
746 if (connected)
747 printf(" of %s", connected);
748 puts(", ");
749
750 return fsl_pci_init_port(info, hose, busno);
751}
752
753#if defined(CONFIG_FSL_CORENET)
754#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
755 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
756 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
757 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
758 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
759#else
760 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
761 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
762 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
763 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
764#endif
765 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
766#elif defined(CONFIG_MPC85xx)
767 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
768 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
769 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
770 #define _DEVDISR_PCIE4 0
771 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
772#elif defined(CONFIG_MPC86xx)
773 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
774 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
775 #define _DEVDISR_PCIE3 0
776 #define _DEVDISR_PCIE4 0
777 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
778 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
779#else
780#error "No defines for DEVDISR_PCIE"
781#endif
782
783
784static const char *__board_serdes_name(enum srds_prtcl device)
785{
786 switch (device) {
787#ifdef CONFIG_SYS_PCIE1_NAME
788 case PCIE1:
789 return CONFIG_SYS_PCIE1_NAME;
790#endif
791#ifdef CONFIG_SYS_PCIE2_NAME
792 case PCIE2:
793 return CONFIG_SYS_PCIE2_NAME;
794#endif
795#ifdef CONFIG_SYS_PCIE3_NAME
796 case PCIE3:
797 return CONFIG_SYS_PCIE3_NAME;
798#endif
799#ifdef CONFIG_SYS_PCIE4_NAME
800 case PCIE4:
801 return CONFIG_SYS_PCIE4_NAME;
802#endif
803 default:
804 return NULL;
805 }
806
807 return NULL;
808}
809
810__attribute__((weak, alias("__board_serdes_name"))) const char *
811board_serdes_name(enum srds_prtcl device);
812
813static u32 devdisr_mask[] = {
814 _DEVDISR_PCIE1,
815 _DEVDISR_PCIE2,
816 _DEVDISR_PCIE3,
817 _DEVDISR_PCIE4,
818};
819
820int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
821 struct fsl_pci_info *pci_info)
822{
823 struct pci_controller *hose;
824 int num = dev - PCIE1;
825
826 hose = calloc(1, sizeof(struct pci_controller));
827 if (!hose)
828 return busno;
829
830 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
831 busno = fsl_configure_pcie(pci_info, hose,
832 board_serdes_name(dev), busno);
833 } else {
834 printf("PCIe%d: disabled\n", num + 1);
835 }
836
837 return busno;
838}
839
840int fsl_pcie_init_board(int busno)
841{
842 struct fsl_pci_info pci_info;
843 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
844 u32 devdisr;
845 u32 *addr;
846
847#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
848 addr = &gur->devdisr3;
849#else
850 addr = &gur->devdisr;
851#endif
852 devdisr = in_be32(addr);
853
854#ifdef CONFIG_PCIE1
855 SET_STD_PCIE_INFO(pci_info, 1);
856 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
857#else
858 setbits_be32(addr, _DEVDISR_PCIE1);
859#endif
860
861#ifdef CONFIG_PCIE2
862 SET_STD_PCIE_INFO(pci_info, 2);
863 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
864#else
865 setbits_be32(addr, _DEVDISR_PCIE2);
866#endif
867
868#ifdef CONFIG_PCIE3
869 SET_STD_PCIE_INFO(pci_info, 3);
870 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
871#else
872 setbits_be32(addr, _DEVDISR_PCIE3);
873#endif
874
875#ifdef CONFIG_PCIE4
876 SET_STD_PCIE_INFO(pci_info, 4);
877 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
878#else
879 setbits_be32(addr, _DEVDISR_PCIE4);
880#endif
881
882 return busno;
883}
884#else
885int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
886 struct fsl_pci_info *pci_info)
887{
888 return busno;
889}
890
891int fsl_pcie_init_board(int busno)
892{
893 return busno;
894}
895#endif
896
897#ifdef CONFIG_OF_BOARD_SETUP
898#include <linux/libfdt.h>
899#include <fdt_support.h>
900
901void ft_fsl_pci_setup(void *blob, const char *pci_compat,
902 unsigned long ctrl_addr)
903{
904 int off;
905 u32 bus_range[2];
906 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
907 struct pci_controller *hose;
908
909 hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
910
911
912 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
913 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
914
915 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
916
917 if (off < 0)
918 return;
919
920
921 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
922 fdt_del_node(blob, off);
923 } else {
924 bus_range[0] = 0;
925 bus_range[1] = hose->last_busno - hose->first_busno;
926 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
927 fdt_pci_dma_ranges(blob, off, hose);
928 }
929}
930#endif
931
