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10#include <common.h>
11#include <dm.h>
12#include <log.h>
13#include <pci.h>
14#include <asm/arch/fsl_serdes.h>
15#include <asm/io.h>
16#include <errno.h>
17#ifdef CONFIG_OF_BOARD_SETUP
18#include <linux/libfdt.h>
19#include <fdt_support.h>
20#ifdef CONFIG_ARM
21#include <asm/arch/clock.h>
22#endif
23#include "pcie_layerscape_gen4.h"
24#include "pcie_layerscape_fixup_common.h"
25
26#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
27
28
29
30static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
31{
32 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
33 return pcie->next_lut_index++;
34
35 return -ENOSPC;
36}
37
38
39
40
41static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
42 u32 devid, u32 streamid)
43{
44
45 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
46 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
47}
48
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54
55
56
57static void fdt_pcie_set_msi_map_entry_ls_gen4(void *blob,
58 struct ls_pcie_g4 *pcie,
59 u32 devid, u32 streamid)
60{
61 u32 *prop;
62 u32 phandle;
63 int nodeoff;
64
65#ifdef CONFIG_FSL_PCIE_COMPAT
66 nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
67 pcie->ccsr_res.start);
68#else
69#error "No CONFIG_FSL_PCIE_COMPAT defined"
70#endif
71 if (nodeoff < 0) {
72 debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
73 return;
74 }
75
76
77 prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
78 if (!prop) {
79 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
80 __func__, pcie->idx);
81 return;
82 }
83 phandle = fdt32_to_cpu(*prop);
84
85
86 fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
87 fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
88 fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
89 fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
90}
91
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98
99
100static void fdt_pcie_set_iommu_map_entry_ls_gen4(void *blob,
101 struct ls_pcie_g4 *pcie,
102 u32 devid, u32 streamid)
103{
104 u32 *prop;
105 u32 iommu_map[4];
106 int nodeoff;
107 int lenp;
108
109#ifdef CONFIG_FSL_PCIE_COMPAT
110 nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
111 pcie->ccsr_res.start);
112#else
113#error "No CONFIG_FSL_PCIE_COMPAT defined"
114#endif
115 if (nodeoff < 0) {
116 debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
117 return;
118 }
119
120
121 prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp);
122 if (!prop) {
123 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
124 __func__, pcie->idx);
125 return;
126 }
127
128
129 iommu_map[0] = cpu_to_fdt32(devid);
130 iommu_map[1] = *++prop;
131 iommu_map[2] = cpu_to_fdt32(streamid);
132 iommu_map[3] = cpu_to_fdt32(1);
133
134 if (devid == 0)
135 fdt_setprop_inplace(blob, nodeoff, "iommu-map", iommu_map, 16);
136 else
137 fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
138}
139
140static void fdt_fixup_pcie_ls_gen4(void *blob)
141{
142 struct udevice *dev, *bus;
143 struct ls_pcie_g4 *pcie;
144 int streamid;
145 int index;
146 pci_dev_t bdf;
147
148
149 for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
150 for (bus = dev; device_is_on_pci_bus(bus);)
151 bus = bus->parent;
152 pcie = dev_get_priv(bus);
153
154 streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
155 if (streamid < 0) {
156 debug("ERROR: no stream ids free\n");
157 continue;
158 } else {
159 pcie->stream_id_cur++;
160 }
161
162 index = ls_pcie_g4_next_lut_index(pcie);
163 if (index < 0) {
164 debug("ERROR: no LUT indexes free\n");
165 continue;
166 }
167
168
169 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
170
171 ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
172
173 fdt_pcie_set_msi_map_entry_ls_gen4(blob, pcie, bdf >> 8,
174 streamid);
175
176 fdt_pcie_set_iommu_map_entry_ls_gen4(blob, pcie, bdf >> 8,
177 streamid);
178 }
179}
180#endif
181
182static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
183{
184 int off;
185
186 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
187 pcie->ccsr_res.start);
188
189 if (off < 0) {
190 debug("%s: ERROR: failed to find pcie compatiable\n",
191 __func__);
192 return;
193 }
194
195 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
196 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
197 else
198 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
199}
200
201static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
202{
203 int off;
204
205#ifdef CONFIG_FSL_PCIE_COMPAT
206 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
207 pcie->ccsr_res.start);
208#else
209#error "No CONFIG_FSL_PCIE_COMPAT defined"
210#endif
211 if (off < 0) {
212 debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
213 return;
214 }
215
216 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
217 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
218 else
219 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
220}
221
222static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
223{
224 ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
225 ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
226}
227
228
229void ft_pci_setup_ls_gen4(void *blob, struct bd_info *bd)
230{
231 struct ls_pcie_g4 *pcie;
232
233 list_for_each_entry(pcie, &ls_pcie_g4_list, list)
234 ft_pcie_layerscape_gen4_setup(blob, pcie);
235
236#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
237 fdt_fixup_pcie_ls_gen4(blob);
238#endif
239}
240
241#else
242void ft_pci_setup_ls_gen4(void *blob, struct bd_info *bd)
243{
244}
245#endif
246
