LXR uboot/drivers/sysreset/sysreset

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
   4 *
   5 * Generic reset driver for x86 processor
   6 */
   7
   8#include <common.h>
   9#include <dm.h>
  10#include <efi_loader.h>
  11#include <pch.h>
  12#include <sysreset.h>
  13#include <acpi/acpi_s3.h>
  14#include <asm/io.h>
  15#include <asm/processor.h>
  16
  17struct x86_sysreset_platdata {
  18        struct udevice *pch;
  19};
  20
  21/*
  22 * Power down the machine by using the power management sleep control
  23 * of the chipset. This will currently only work on Intel chipsets.
  24 * However, adapting it to new chipsets is fairly simple. You will
  25 * have to find the IO address of the power management register block
  26 * in your southbridge, and look up the appropriate SLP_TYP_S5 value
  27 * from your southbridge's data sheet.
  28 *
  29 * This function never returns.
  30 */
  31int pch_sysreset_power_off(struct udevice *dev)
  32{
  33        struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
  34        struct pch_pmbase_info pm;
  35        u32 reg32;
  36        int ret;
  37
  38        if (!plat->pch)
  39                return -ENOENT;
  40        ret = pch_ioctl(plat->pch, PCH_REQ_PMBASE_INFO, &pm, sizeof(pm));
  41        if (ret)
  42                return ret;
  43
  44        /*
  45         * Mask interrupts or system might stay in a coma, not executing code
  46         * anymore, but not powered off either.
  47         */
  48        asm("cli");
  49
  50        /*
  51         * Avoid any GPI waking the system from S5* or the system might stay in
  52         * a coma
  53         */
  54        outl(0x00000000, pm.base + pm.gpio0_en_ofs);
  55
  56        /* Clear Power Button Status */
  57        outw(PWRBTN_STS, pm.base + pm.pm1_sts_ofs);
  58
  59        /* PMBASE + 4, Bit 10-12, Sleeping Type, * set to 111 -> S5, soft_off */
  60        reg32 = inl(pm.base + pm.pm1_cnt_ofs);
  61
  62        /* Set Sleeping Type to S5 (poweroff) */
  63        reg32 &= ~(SLP_EN | SLP_TYP);
  64        reg32 |= SLP_TYP_S5;
  65        outl(reg32, pm.base + pm.pm1_cnt_ofs);
  66
  67        /* Now set the Sleep Enable bit */
  68        reg32 |= SLP_EN;
  69        outl(reg32, pm.base + pm.pm1_cnt_ofs);
  70
  71        for (;;)
  72                asm("hlt");
  73}
  74
  75static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
  76{
  77        int value;
  78        int ret;
  79
  80        switch (type) {
  81        case SYSRESET_WARM:
  82                value = SYS_RST | RST_CPU;
  83                break;
  84        case SYSRESET_COLD:
  85                value = SYS_RST | RST_CPU | FULL_RST;
  86                break;
  87        case SYSRESET_POWER_OFF:
  88                ret = pch_sysreset_power_off(dev);
  89                if (ret)
  90                        return ret;
  91                return -EINPROGRESS;
  92        default:
  93                return -ENOSYS;
  94        }
  95
  96        outb(value, IO_PORT_RESET);
  97
  98        return -EINPROGRESS;
  99}
 100
 101static int x86_sysreset_get_last(struct udevice *dev)
 102{
 103        return SYSRESET_POWER;
 104}
 105
 106#ifdef CONFIG_EFI_LOADER
 107void __efi_runtime EFIAPI efi_reset_system(
 108                        enum efi_reset_type reset_type,
 109                        efi_status_t reset_status,
 110                        unsigned long data_size, void *reset_data)
 111{
 112        int value;
 113
 114        /*
 115         * inline this code since we are not caused in the context of a
 116         * udevice and passing NULL to x86_sysreset_request() is too horrible.
 117         */
 118        if (reset_type == EFI_RESET_COLD ||
 119                 reset_type == EFI_RESET_PLATFORM_SPECIFIC)
 120                value = SYS_RST | RST_CPU | FULL_RST;
 121        else /* assume EFI_RESET_WARM since we cannot return an error */
 122                value = SYS_RST | RST_CPU;
 123        outb(value, IO_PORT_RESET);
 124
 125        /* TODO EFI_RESET_SHUTDOWN */
 126
 127        while (1) { }
 128}
 129#endif
 130
 131static int x86_sysreset_probe(struct udevice *dev)
 132{
 133        struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
 134
 135        /* Locate the PCH if there is one. It isn't essential */
 136        uclass_first_device(UCLASS_PCH, &plat->pch);
 137
 138        return 0;
 139}
 140
 141static const struct udevice_id x86_sysreset_ids[] = {
 142        { .compatible = "x86,reset" },
 143        { }
 144};
 145
 146static struct sysreset_ops x86_sysreset_ops = {
 147        .request = x86_sysreset_request,
 148        .get_last = x86_sysreset_get_last,
 149};
 150
 151U_BOOT_DRIVER(x86_reset) = {
 152        .name = "x86_reset",
 153        .id = UCLASS_SYSRESET,
 154        .of_match = x86_sysreset_ids,
 155        .ops = &x86_sysreset_ops,
 156        .probe = x86_sysreset_probe,
 157        .platdata_auto_alloc_size       = sizeof(struct x86_sysreset_platdata),
 158};
 159