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20#include <common.h>
21#include <cpu_func.h>
22#include <log.h>
23#include <linux/bug.h>
24
25static u8 clear_feature_num;
26int clear_feature_flag;
27
28
29#define GET_MAX_LUN_REQUEST 0xFE
30#define BOT_RESET_REQUEST 0xFF
31
32static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
33{
34 u32 ep_ctrl;
35
36 writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), ®->in_endp[EP0_CON].diepdma);
37 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
38
39 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
40 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
41 ®->in_endp[EP0_CON].diepctl);
42
43 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
44 __func__, readl(®->in_endp[EP0_CON].diepctl));
45 dev->ep0state = WAIT_FOR_IN_COMPLETE;
46}
47
48static void dwc2_udc_pre_setup(void)
49{
50 u32 ep_ctrl;
51
52 debug_cond(DEBUG_IN_EP,
53 "%s : Prepare Setup packets.\n", __func__);
54
55 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
56 ®->out_endp[EP0_CON].doeptsiz);
57 writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), ®->out_endp[EP0_CON].doepdma);
58
59 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
60 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
61
62 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
63 __func__, readl(®->in_endp[EP0_CON].diepctl));
64 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
65 __func__, readl(®->out_endp[EP0_CON].doepctl));
66
67}
68
69static inline void dwc2_ep0_complete_out(void)
70{
71 u32 ep_ctrl;
72
73 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
74 __func__, readl(®->in_endp[EP0_CON].diepctl));
75 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
76 __func__, readl(®->out_endp[EP0_CON].doepctl));
77
78 debug_cond(DEBUG_IN_EP,
79 "%s : Prepare Complete Out packet.\n", __func__);
80
81 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
82 ®->out_endp[EP0_CON].doeptsiz);
83 writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), ®->out_endp[EP0_CON].doepdma);
84
85 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
86 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
87 ®->out_endp[EP0_CON].doepctl);
88
89 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
90 __func__, readl(®->in_endp[EP0_CON].diepctl));
91 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
92 __func__, readl(®->out_endp[EP0_CON].doepctl));
93
94}
95
96
97static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
98{
99 u32 *buf, ctrl;
100 u32 length, pktcnt;
101 u32 ep_num = ep_index(ep);
102
103 buf = req->req.buf + req->req.actual;
104 length = min_t(u32, req->req.length - req->req.actual,
105 ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
106
107 ep->len = length;
108 ep->dma_buf = buf;
109
110 if (ep_num == EP0_CON || length == 0)
111 pktcnt = 1;
112 else
113 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
114
115 ctrl = readl(®->out_endp[ep_num].doepctl);
116
117 invalidate_dcache_range((unsigned long) ep->dma_buf,
118 (unsigned long) ep->dma_buf +
119 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
120
121 writel(phys_to_bus((unsigned long)ep->dma_buf), ®->out_endp[ep_num].doepdma);
122 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
123 ®->out_endp[ep_num].doeptsiz);
124 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
125
126 debug_cond(DEBUG_OUT_EP != 0,
127 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
128 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
129 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
130 __func__, ep_num,
131 readl(®->out_endp[ep_num].doepdma),
132 readl(®->out_endp[ep_num].doeptsiz),
133 readl(®->out_endp[ep_num].doepctl),
134 buf, pktcnt, length);
135 return 0;
136
137}
138
139static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
140{
141 u32 *buf, ctrl = 0;
142 u32 length, pktcnt;
143 u32 ep_num = ep_index(ep);
144
145 buf = req->req.buf + req->req.actual;
146 length = req->req.length - req->req.actual;
147
148 if (ep_num == EP0_CON)
149 length = min(length, (u32)ep_maxpacket(ep));
150
151 ep->len = length;
152 ep->dma_buf = buf;
153
154 flush_dcache_range((unsigned long) ep->dma_buf,
155 (unsigned long) ep->dma_buf +
156 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
157
158 if (length == 0)
159 pktcnt = 1;
160 else
161 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
162
163
164 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
165 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
166 while (readl(®->grstctl) & TX_FIFO_FLUSH)
167 ;
168
169 writel(phys_to_bus((unsigned long)ep->dma_buf), ®->in_endp[ep_num].diepdma);
170 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
171 ®->in_endp[ep_num].dieptsiz);
172
173 ctrl = readl(®->in_endp[ep_num].diepctl);
174
175
176 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
177 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
178
179
180 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
181
182 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
183
184 debug_cond(DEBUG_IN_EP,
185 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
186 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
187 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
188 __func__, ep_num,
189 readl(®->in_endp[ep_num].diepdma),
190 readl(®->in_endp[ep_num].dieptsiz),
191 readl(®->in_endp[ep_num].diepctl),
192 buf, pktcnt, length);
193
194 return length;
195}
196
197static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
198{
199 struct dwc2_ep *ep = &dev->ep[ep_num];
200 struct dwc2_request *req = NULL;
201 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
202
203 if (list_empty(&ep->queue)) {
204 debug_cond(DEBUG_OUT_EP != 0,
205 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
206 __func__, ep_num);
207 return;
208
209 }
210
211 req = list_entry(ep->queue.next, struct dwc2_request, queue);
212 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
213
214 if (ep_num == EP0_CON)
215 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
216 else
217 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
218
219 xfer_size = ep->len - xfer_size;
220
221
222
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224
225
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227
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229
230
231
232
233
234
235 invalidate_dcache_range((unsigned long) ep->dma_buf,
236 (unsigned long) ep->dma_buf +
237 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
238
239 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
240 is_short = !!(xfer_size % ep->ep.maxpacket);
241
242 debug_cond(DEBUG_OUT_EP != 0,
243 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
244 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
245 __func__, ep_num, req->req.actual, req->req.length,
246 is_short, ep_tsr, req->req.length - req->req.actual);
247
248 if (is_short || req->req.actual == req->req.length) {
249 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
250 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
251 dwc2_udc_ep0_zlp(dev);
252
253 dev->ep0state = WAIT_FOR_IN_COMPLETE;
254 } else {
255 done(ep, req, 0);
256
257 if (!list_empty(&ep->queue)) {
258 req = list_entry(ep->queue.next,
259 struct dwc2_request, queue);
260 debug_cond(DEBUG_OUT_EP != 0,
261 "%s: Next Rx request start...\n",
262 __func__);
263 setdma_rx(ep, req);
264 }
265 }
266 } else
267 setdma_rx(ep, req);
268}
269
270static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
271{
272 struct dwc2_ep *ep = &dev->ep[ep_num];
273 struct dwc2_request *req;
274 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
275 u32 last;
276
277 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
278 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
279 dwc2_ep0_complete_out();
280 return;
281 }
282
283 if (list_empty(&ep->queue)) {
284 debug_cond(DEBUG_IN_EP,
285 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
286 __func__, ep_num);
287 return;
288
289 }
290
291 req = list_entry(ep->queue.next, struct dwc2_request, queue);
292
293 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
294
295 xfer_size = ep->len;
296 is_short = (xfer_size < ep->ep.maxpacket);
297 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
298
299 debug_cond(DEBUG_IN_EP,
300 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
301 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
302 __func__, ep_num, req->req.actual, req->req.length,
303 is_short, ep_tsr, req->req.length - req->req.actual);
304
305 if (ep_num == 0) {
306 if (dev->ep0state == DATA_STATE_XMIT) {
307 debug_cond(DEBUG_IN_EP,
308 "%s: ep_num = %d, ep0stat =="
309 "DATA_STATE_XMIT\n",
310 __func__, ep_num);
311 last = write_fifo_ep0(ep, req);
312 if (last)
313 dev->ep0state = WAIT_FOR_COMPLETE;
314 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
315 debug_cond(DEBUG_IN_EP,
316 "%s: ep_num = %d, completing request\n",
317 __func__, ep_num);
318 done(ep, req, 0);
319 dev->ep0state = WAIT_FOR_SETUP;
320 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
321 debug_cond(DEBUG_IN_EP,
322 "%s: ep_num = %d, completing request\n",
323 __func__, ep_num);
324 done(ep, req, 0);
325 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
326 dwc2_ep0_complete_out();
327 } else {
328 debug_cond(DEBUG_IN_EP,
329 "%s: ep_num = %d, invalid ep state\n",
330 __func__, ep_num);
331 }
332 return;
333 }
334
335 if (req->req.actual == req->req.length)
336 done(ep, req, 0);
337
338 if (!list_empty(&ep->queue)) {
339 req = list_entry(ep->queue.next, struct dwc2_request, queue);
340 debug_cond(DEBUG_IN_EP,
341 "%s: Next Tx request start...\n", __func__);
342 setdma_tx(ep, req);
343 }
344}
345
346static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
347{
348 struct dwc2_ep *ep = &dev->ep[ep_num];
349 struct dwc2_request *req;
350
351 debug_cond(DEBUG_IN_EP,
352 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
353
354 if (!list_empty(&ep->queue)) {
355 req = list_entry(ep->queue.next, struct dwc2_request, queue);
356 debug_cond(DEBUG_IN_EP,
357 "%s: Next Tx request(0x%p) start...\n",
358 __func__, req);
359
360 if (ep_is_in(ep))
361 setdma_tx(ep, req);
362 else
363 setdma_rx(ep, req);
364 } else {
365 debug_cond(DEBUG_IN_EP,
366 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
367
368 return;
369 }
370
371}
372
373static void process_ep_in_intr(struct dwc2_udc *dev)
374{
375 u32 ep_intr, ep_intr_status;
376 u8 ep_num = 0;
377
378 ep_intr = readl(®->daint);
379 debug_cond(DEBUG_IN_EP,
380 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
381
382 ep_intr &= DAINT_MASK;
383
384 while (ep_intr) {
385 if (ep_intr & DAINT_IN_EP_INT(1)) {
386 ep_intr_status = readl(®->in_endp[ep_num].diepint);
387 debug_cond(DEBUG_IN_EP,
388 "\tEP%d-IN : DIEPINT = 0x%x\n",
389 ep_num, ep_intr_status);
390
391
392 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
393
394 if (ep_intr_status & TRANSFER_DONE) {
395 complete_tx(dev, ep_num);
396
397 if (ep_num == 0) {
398 if (dev->ep0state ==
399 WAIT_FOR_IN_COMPLETE)
400 dev->ep0state = WAIT_FOR_SETUP;
401
402 if (dev->ep0state == WAIT_FOR_SETUP)
403 dwc2_udc_pre_setup();
404
405
406
407 if (clear_feature_flag == 1) {
408 dwc2_udc_check_tx_queue(dev,
409 clear_feature_num);
410 clear_feature_flag = 0;
411 }
412 }
413 }
414 }
415 ep_num++;
416 ep_intr >>= 1;
417 }
418}
419
420static void process_ep_out_intr(struct dwc2_udc *dev)
421{
422 u32 ep_intr, ep_intr_status;
423 u8 ep_num = 0;
424 u32 ep_tsr = 0, xfer_size = 0;
425 u32 epsiz_reg = reg->out_endp[ep_num].doeptsiz;
426 u32 req_size = sizeof(struct usb_ctrlrequest);
427
428 ep_intr = readl(®->daint);
429 debug_cond(DEBUG_OUT_EP != 0,
430 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
431 __func__, ep_intr);
432
433 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
434
435 while (ep_intr) {
436 if (ep_intr & 0x1) {
437 ep_intr_status = readl(®->out_endp[ep_num].doepint);
438 debug_cond(DEBUG_OUT_EP != 0,
439 "\tEP%d-OUT : DOEPINT = 0x%x\n",
440 ep_num, ep_intr_status);
441
442
443 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
444
445 if (ep_num == 0) {
446 if (ep_intr_status & TRANSFER_DONE) {
447 ep_tsr = readl(&epsiz_reg);
448 xfer_size = ep_tsr &
449 DOEPT_SIZ_XFER_SIZE_MAX_EP0;
450
451 if (xfer_size == req_size &&
452 dev->ep0state == WAIT_FOR_SETUP) {
453 dwc2_udc_pre_setup();
454 } else if (dev->ep0state !=
455 WAIT_FOR_OUT_COMPLETE) {
456 complete_rx(dev, ep_num);
457 } else {
458 dev->ep0state = WAIT_FOR_SETUP;
459 dwc2_udc_pre_setup();
460 }
461 }
462
463 if (ep_intr_status &
464 CTRL_OUT_EP_SETUP_PHASE_DONE) {
465 debug_cond(DEBUG_OUT_EP != 0,
466 "SETUP packet arrived\n");
467 dwc2_handle_ep0(dev);
468 }
469 } else {
470 if (ep_intr_status & TRANSFER_DONE)
471 complete_rx(dev, ep_num);
472 }
473 }
474 ep_num++;
475 ep_intr >>= 1;
476 }
477}
478
479
480
481
482static int dwc2_udc_irq(int irq, void *_dev)
483{
484 struct dwc2_udc *dev = _dev;
485 u32 intr_status, gotgint;
486 u32 usb_status, gintmsk;
487 unsigned long flags = 0;
488
489 spin_lock_irqsave(&dev->lock, flags);
490
491 intr_status = readl(®->gintsts);
492 gintmsk = readl(®->gintmsk);
493
494 debug_cond(DEBUG_ISR,
495 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
496 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
497 __func__, intr_status, state_names[dev->ep0state], gintmsk,
498 readl(®->daint), readl(®->daintmsk));
499
500 if (!intr_status) {
501 spin_unlock_irqrestore(&dev->lock, flags);
502 return IRQ_HANDLED;
503 }
504
505 if (intr_status & INT_ENUMDONE) {
506 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
507
508 writel(INT_ENUMDONE, ®->gintsts);
509 usb_status = (readl(®->dsts) & 0x6);
510
511 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
512 debug_cond(DEBUG_ISR,
513 "\t\tFull Speed Detection\n");
514 set_max_pktsize(dev, USB_SPEED_FULL);
515
516 } else {
517 debug_cond(DEBUG_ISR,
518 "\t\tHigh Speed Detection : 0x%x\n",
519 usb_status);
520 set_max_pktsize(dev, USB_SPEED_HIGH);
521 }
522 }
523
524 if (intr_status & INT_EARLY_SUSPEND) {
525 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
526 writel(INT_EARLY_SUSPEND, ®->gintsts);
527 }
528
529 if (intr_status & INT_SUSPEND) {
530 usb_status = readl(®->dsts);
531 debug_cond(DEBUG_ISR,
532 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
533 writel(INT_SUSPEND, ®->gintsts);
534
535 if (dev->gadget.speed != USB_SPEED_UNKNOWN
536 && dev->driver) {
537 if (dev->driver->suspend)
538 dev->driver->suspend(&dev->gadget);
539 }
540 }
541
542 if (intr_status & INT_OTG) {
543 gotgint = readl(®->gotgint);
544 debug_cond(DEBUG_ISR,
545 "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
546
547 if (gotgint & GOTGINT_SES_END_DET) {
548 debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
549
550 if (dev->driver->disconnect) {
551 spin_unlock_irqrestore(&dev->lock, flags);
552 dev->driver->disconnect(&dev->gadget);
553 spin_lock_irqsave(&dev->lock, flags);
554 }
555 }
556 writel(gotgint, ®->gotgint);
557 }
558
559 if (intr_status & INT_RESUME) {
560 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
561 writel(INT_RESUME, ®->gintsts);
562
563 if (dev->gadget.speed != USB_SPEED_UNKNOWN
564 && dev->driver
565 && dev->driver->resume) {
566
567 dev->driver->resume(&dev->gadget);
568 }
569 }
570
571 if (intr_status & INT_RESET) {
572 usb_status = readl(®->gotgctl);
573 debug_cond(DEBUG_ISR,
574 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
575 writel(INT_RESET, ®->gintsts);
576
577 if ((usb_status & 0xc0000) == (0x3 << 18)) {
578 if (reset_available) {
579 debug_cond(DEBUG_ISR,
580 "\t\tOTG core got reset (%d)!!\n",
581 reset_available);
582 reconfig_usbd(dev);
583 dev->ep0state = WAIT_FOR_SETUP;
584 reset_available = 0;
585 dwc2_udc_pre_setup();
586 } else
587 reset_available = 1;
588
589 } else {
590 reset_available = 1;
591 debug_cond(DEBUG_ISR,
592 "\t\tRESET handling skipped\n");
593 }
594 }
595
596 if (intr_status & INT_IN_EP)
597 process_ep_in_intr(dev);
598
599 if (intr_status & INT_OUT_EP)
600 process_ep_out_intr(dev);
601
602 spin_unlock_irqrestore(&dev->lock, flags);
603
604 return IRQ_HANDLED;
605}
606
607
608
609
610static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
611 gfp_t gfp_flags)
612{
613 struct dwc2_request *req;
614 struct dwc2_ep *ep;
615 struct dwc2_udc *dev;
616 unsigned long flags = 0;
617 u32 ep_num, gintsts;
618
619 req = container_of(_req, struct dwc2_request, req);
620 if (unlikely(!_req || !_req->complete || !_req->buf
621 || !list_empty(&req->queue))) {
622
623 debug("%s: bad params\n", __func__);
624 return -EINVAL;
625 }
626
627 ep = container_of(_ep, struct dwc2_ep, ep);
628
629 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
630
631 debug("%s: bad ep: %s, %d, %p\n", __func__,
632 ep->ep.name, !ep->desc, _ep);
633 return -EINVAL;
634 }
635
636 ep_num = ep_index(ep);
637 dev = ep->dev;
638 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
639
640 debug("%s: bogus device state %p\n", __func__, dev->driver);
641 return -ESHUTDOWN;
642 }
643
644 spin_lock_irqsave(&dev->lock, flags);
645
646 _req->status = -EINPROGRESS;
647 _req->actual = 0;
648
649
650 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
651 "Q empty = %d, stopped = %d\n",
652 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
653 _req, _req->length, _req->buf,
654 list_empty(&ep->queue), ep->stopped);
655
656#ifdef DEBUG
657 {
658 int i, len = _req->length;
659
660 printf("pkt = ");
661 if (len > 64)
662 len = 64;
663 for (i = 0; i < len; i++) {
664 printf("%02x", ((u8 *)_req->buf)[i]);
665 if ((i & 7) == 7)
666 printf(" ");
667 }
668 printf("\n");
669 }
670#endif
671
672 if (list_empty(&ep->queue) && !ep->stopped) {
673
674 if (ep_num == 0) {
675
676 list_add_tail(&req->queue, &ep->queue);
677 dwc2_ep0_kick(dev, ep);
678 req = 0;
679
680 } else if (ep_is_in(ep)) {
681 gintsts = readl(®->gintsts);
682 debug_cond(DEBUG_IN_EP,
683 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
684 __func__, gintsts);
685
686 setdma_tx(ep, req);
687 } else {
688 gintsts = readl(®->gintsts);
689 debug_cond(DEBUG_OUT_EP != 0,
690 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
691 __func__, gintsts);
692
693 setdma_rx(ep, req);
694 }
695 }
696
697
698 if (likely(req != 0))
699 list_add_tail(&req->queue, &ep->queue);
700
701 spin_unlock_irqrestore(&dev->lock, flags);
702
703 return 0;
704}
705
706
707
708
709
710
711static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
712{
713 u32 max;
714 unsigned count;
715 int is_last;
716
717 max = ep_maxpacket(ep);
718
719 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
720
721 count = setdma_tx(ep, req);
722
723
724 if (likely(count != max))
725 is_last = 1;
726 else {
727 if (likely(req->req.length != req->req.actual + count)
728 || req->req.zero)
729 is_last = 0;
730 else
731 is_last = 1;
732 }
733
734 debug_cond(DEBUG_EP0 != 0,
735 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
736 ep->ep.name, count,
737 is_last ? "/L" : "",
738 req->req.length - req->req.actual - count, req);
739
740
741 if (is_last) {
742 ep->dev->ep0state = WAIT_FOR_SETUP;
743 return 1;
744 }
745
746 return 0;
747}
748
749static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
750{
751 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
752 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
753
754 debug_cond(DEBUG_EP0 != 0,
755 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
756 max, ep_index(ep), cp);
757
758 return max;
759}
760
761
762
763
764
765
766
767
768static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
769{
770 u32 ctrl = readl(®->dcfg);
771 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
772
773 dwc2_udc_ep0_zlp(dev);
774
775 debug_cond(DEBUG_EP0 != 0,
776 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
777 __func__, address, readl(®->dcfg));
778
779 dev->usb_address = address;
780}
781
782static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
783{
784 struct dwc2_udc *dev;
785 u32 ep_ctrl = 0;
786
787 dev = ep->dev;
788 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
789
790
791 if (ep_ctrl & DEPCTL_EPENA)
792 ep_ctrl |= DEPCTL_EPDIS;
793
794 ep_ctrl |= DEPCTL_STALL;
795
796 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
797
798 debug_cond(DEBUG_EP0 != 0,
799 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
800 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
801
802
803
804
805 dev->ep0state = WAIT_FOR_SETUP;
806
807 dwc2_udc_pre_setup();
808}
809
810static void dwc2_ep0_read(struct dwc2_udc *dev)
811{
812 struct dwc2_request *req;
813 struct dwc2_ep *ep = &dev->ep[0];
814
815 if (!list_empty(&ep->queue)) {
816 req = list_entry(ep->queue.next, struct dwc2_request, queue);
817
818 } else {
819 debug("%s: ---> BUG\n", __func__);
820 BUG();
821 return;
822 }
823
824 debug_cond(DEBUG_EP0 != 0,
825 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
826 __func__, req, req->req.length, req->req.actual);
827
828 if (req->req.length == 0) {
829
830
831
832 ep->len = 0;
833 dwc2_udc_ep0_zlp(dev);
834
835 debug_cond(DEBUG_EP0 != 0,
836 "%s: req.length = 0, bRequest = %d\n",
837 __func__, usb_ctrl->bRequest);
838 return;
839 }
840
841 setdma_rx(ep, req);
842}
843
844
845
846
847static int dwc2_ep0_write(struct dwc2_udc *dev)
848{
849 struct dwc2_request *req;
850 struct dwc2_ep *ep = &dev->ep[0];
851 int ret, need_zlp = 0;
852
853 if (list_empty(&ep->queue))
854 req = 0;
855 else
856 req = list_entry(ep->queue.next, struct dwc2_request, queue);
857
858 if (!req) {
859 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
860 return 0;
861 }
862
863 debug_cond(DEBUG_EP0 != 0,
864 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
865 __func__, req, req->req.length, req->req.actual);
866
867 if (req->req.length - req->req.actual == ep0_fifo_size) {
868
869
870 need_zlp = 1;
871 }
872
873 ret = write_fifo_ep0(ep, req);
874
875 if ((ret == 1) && !need_zlp) {
876
877 dev->ep0state = WAIT_FOR_COMPLETE;
878 debug_cond(DEBUG_EP0 != 0,
879 "%s: finished, waiting for status\n", __func__);
880
881 } else {
882 dev->ep0state = DATA_STATE_XMIT;
883 debug_cond(DEBUG_EP0 != 0,
884 "%s: not finished\n", __func__);
885 }
886
887 return 1;
888}
889
890static int dwc2_udc_get_status(struct dwc2_udc *dev,
891 struct usb_ctrlrequest *crq)
892{
893 u8 ep_num = crq->wIndex & 0x7F;
894 u16 g_status = 0;
895 u32 ep_ctrl;
896
897 debug_cond(DEBUG_SETUP != 0,
898 "%s: *** USB_REQ_GET_STATUS\n", __func__);
899 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
900 switch (crq->bRequestType & USB_RECIP_MASK) {
901 case USB_RECIP_INTERFACE:
902 g_status = 0;
903 debug_cond(DEBUG_SETUP != 0,
904 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
905 g_status);
906 break;
907
908 case USB_RECIP_DEVICE:
909 g_status = 0x1;
910 debug_cond(DEBUG_SETUP != 0,
911 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
912 g_status);
913 break;
914
915 case USB_RECIP_ENDPOINT:
916 if (crq->wLength > 2) {
917 debug_cond(DEBUG_SETUP != 0,
918 "\tGET_STATUS:Not support EP or wLength\n");
919 return 1;
920 }
921
922 g_status = dev->ep[ep_num].stopped;
923 debug_cond(DEBUG_SETUP != 0,
924 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
925 g_status);
926
927 break;
928
929 default:
930 return 1;
931 }
932
933 memcpy(usb_ctrl, &g_status, sizeof(g_status));
934
935 flush_dcache_range((unsigned long) usb_ctrl,
936 (unsigned long) usb_ctrl +
937 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
938
939 writel(phys_to_bus(usb_ctrl_dma_addr), ®->in_endp[EP0_CON].diepdma);
940 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
941 ®->in_endp[EP0_CON].dieptsiz);
942
943 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
944 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
945 ®->in_endp[EP0_CON].diepctl);
946 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
947
948 return 0;
949}
950
951static void dwc2_udc_set_nak(struct dwc2_ep *ep)
952{
953 u8 ep_num;
954 u32 ep_ctrl = 0;
955
956 ep_num = ep_index(ep);
957 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
958
959 if (ep_is_in(ep)) {
960 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
961 ep_ctrl |= DEPCTL_SNAK;
962 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
963 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
964 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
965 } else {
966 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
967 ep_ctrl |= DEPCTL_SNAK;
968 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
969 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
970 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
971 }
972
973 return;
974}
975
976
977static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
978{
979 u8 ep_num;
980 u32 ep_ctrl = 0;
981
982 ep_num = ep_index(ep);
983 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
984
985 if (ep_is_in(ep)) {
986 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
987
988
989 if (ep_ctrl & DEPCTL_EPENA)
990 ep_ctrl |= DEPCTL_EPDIS;
991
992 ep_ctrl |= DEPCTL_STALL;
993
994 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
995 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
996 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
997
998 } else {
999 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1000
1001
1002 ep_ctrl |= DEPCTL_STALL;
1003
1004 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1005 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
1006 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1007 }
1008
1009 return;
1010}
1011
1012static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
1013{
1014 u8 ep_num;
1015 u32 ep_ctrl = 0;
1016
1017 ep_num = ep_index(ep);
1018 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1019
1020 if (ep_is_in(ep)) {
1021 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1022
1023
1024 ep_ctrl &= ~DEPCTL_STALL;
1025
1026
1027
1028
1029
1030
1031
1032 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1033 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1034 ep_ctrl |= DEPCTL_SETD0PID;
1035 }
1036
1037 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1038 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1039 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1040
1041 } else {
1042 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1043
1044
1045 ep_ctrl &= ~DEPCTL_STALL;
1046
1047 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1048 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1049 ep_ctrl |= DEPCTL_SETD0PID;
1050 }
1051
1052 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1053 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1054 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1055 }
1056
1057 return;
1058}
1059
1060static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1061{
1062 struct dwc2_ep *ep;
1063 struct dwc2_udc *dev;
1064 unsigned long flags = 0;
1065 u8 ep_num;
1066
1067 ep = container_of(_ep, struct dwc2_ep, ep);
1068 ep_num = ep_index(ep);
1069
1070 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1071 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1072 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1073 return -EINVAL;
1074 }
1075
1076
1077
1078 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1079 debug("%s: %s queue not empty, req = %p\n",
1080 __func__, ep->ep.name,
1081 list_entry(ep->queue.next, struct dwc2_request, queue));
1082
1083 return -EAGAIN;
1084 }
1085
1086 dev = ep->dev;
1087 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1088
1089 spin_lock_irqsave(&dev->lock, flags);
1090
1091 if (value == 0) {
1092 ep->stopped = 0;
1093 dwc2_udc_ep_clear_stall(ep);
1094 } else {
1095 if (ep_num == 0)
1096 dev->ep0state = WAIT_FOR_SETUP;
1097
1098 ep->stopped = 1;
1099 dwc2_udc_ep_set_stall(ep);
1100 }
1101
1102 spin_unlock_irqrestore(&dev->lock, flags);
1103
1104 return 0;
1105}
1106
1107static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1108{
1109 u8 ep_num;
1110 u32 ep_ctrl = 0, daintmsk = 0;
1111
1112 ep_num = ep_index(ep);
1113
1114
1115 if (ep_is_in(ep)) {
1116 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1117 daintmsk = 1 << ep_num;
1118 } else {
1119 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1120 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1121 }
1122
1123 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1124 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1125
1126
1127
1128 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1129 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1130 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1131 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1132 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1133 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1134
1135 if (ep_is_in(ep)) {
1136 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1137 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1138 __func__, ep_num, ep_num,
1139 readl(®->in_endp[ep_num].diepctl));
1140 } else {
1141 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1142 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1143 __func__, ep_num, ep_num,
1144 readl(®->out_endp[ep_num].doepctl));
1145 }
1146 }
1147
1148
1149 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1150 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1151
1152}
1153
1154static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1155{
1156 struct dwc2_udc *dev;
1157 struct dwc2_ep *ep;
1158 u8 ep_num;
1159
1160 ep = container_of(_ep, struct dwc2_ep, ep);
1161 ep_num = ep_index(ep);
1162
1163 dev = ep->dev;
1164 debug_cond(DEBUG_SETUP != 0,
1165 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1166 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1167
1168 if (usb_ctrl->wLength != 0) {
1169 debug_cond(DEBUG_SETUP != 0,
1170 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1171 return 1;
1172 }
1173
1174 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1175 case USB_RECIP_DEVICE:
1176 switch (usb_ctrl->wValue) {
1177 case USB_DEVICE_REMOTE_WAKEUP:
1178 debug_cond(DEBUG_SETUP != 0,
1179 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1180 break;
1181
1182 case USB_DEVICE_TEST_MODE:
1183 debug_cond(DEBUG_SETUP != 0,
1184 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1185
1186 break;
1187 }
1188
1189 dwc2_udc_ep0_zlp(dev);
1190 break;
1191
1192 case USB_RECIP_ENDPOINT:
1193 debug_cond(DEBUG_SETUP != 0,
1194 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1195 usb_ctrl->wValue);
1196
1197 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1198 if (ep_num == 0) {
1199 dwc2_udc_ep0_set_stall(ep);
1200 return 0;
1201 }
1202
1203 dwc2_udc_ep0_zlp(dev);
1204
1205 dwc2_udc_ep_clear_stall(ep);
1206 dwc2_udc_ep_activate(ep);
1207 ep->stopped = 0;
1208
1209 clear_feature_num = ep_num;
1210 clear_feature_flag = 1;
1211 }
1212 break;
1213 }
1214
1215 return 0;
1216}
1217
1218static int dwc2_udc_set_feature(struct usb_ep *_ep)
1219{
1220 struct dwc2_udc *dev;
1221 struct dwc2_ep *ep;
1222 u8 ep_num;
1223
1224 ep = container_of(_ep, struct dwc2_ep, ep);
1225 ep_num = ep_index(ep);
1226 dev = ep->dev;
1227
1228 debug_cond(DEBUG_SETUP != 0,
1229 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1230 __func__, ep_num);
1231
1232 if (usb_ctrl->wLength != 0) {
1233 debug_cond(DEBUG_SETUP != 0,
1234 "\tSET_FEATURE: wLength is not zero.....\n");
1235 return 1;
1236 }
1237
1238 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1239 case USB_RECIP_DEVICE:
1240 switch (usb_ctrl->wValue) {
1241 case USB_DEVICE_REMOTE_WAKEUP:
1242 debug_cond(DEBUG_SETUP != 0,
1243 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1244 break;
1245 case USB_DEVICE_B_HNP_ENABLE:
1246 debug_cond(DEBUG_SETUP != 0,
1247 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1248 break;
1249
1250 case USB_DEVICE_A_HNP_SUPPORT:
1251
1252 debug_cond(DEBUG_SETUP != 0,
1253 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1254 break;
1255
1256 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1257
1258 debug_cond(DEBUG_SETUP != 0,
1259 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1260 break;
1261 }
1262
1263 dwc2_udc_ep0_zlp(dev);
1264 return 0;
1265
1266 case USB_RECIP_INTERFACE:
1267 debug_cond(DEBUG_SETUP != 0,
1268 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1269 break;
1270
1271 case USB_RECIP_ENDPOINT:
1272 debug_cond(DEBUG_SETUP != 0,
1273 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1274 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1275 if (ep_num == 0) {
1276 dwc2_udc_ep0_set_stall(ep);
1277 return 0;
1278 }
1279 ep->stopped = 1;
1280 dwc2_udc_ep_set_stall(ep);
1281 }
1282
1283 dwc2_udc_ep0_zlp(dev);
1284 return 0;
1285 }
1286
1287 return 1;
1288}
1289
1290
1291
1292
1293static void dwc2_ep0_setup(struct dwc2_udc *dev)
1294{
1295 struct dwc2_ep *ep = &dev->ep[0];
1296 int i;
1297 u8 ep_num;
1298
1299
1300 nuke(ep, -EPROTO);
1301
1302
1303 dwc2_fifo_read(ep, usb_ctrl, 8);
1304
1305 debug_cond(DEBUG_SETUP != 0,
1306 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1307 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1308 __func__, usb_ctrl->bRequestType,
1309 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1310 usb_ctrl->bRequest,
1311 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1312
1313#ifdef DEBUG
1314 {
1315 int i, len = sizeof(*usb_ctrl);
1316 char *p = (char *)usb_ctrl;
1317
1318 printf("pkt = ");
1319 for (i = 0; i < len; i++) {
1320 printf("%02x", ((u8 *)p)[i]);
1321 if ((i & 7) == 7)
1322 printf(" ");
1323 }
1324 printf("\n");
1325 }
1326#endif
1327
1328 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1329 usb_ctrl->wLength != 1) {
1330 debug_cond(DEBUG_SETUP != 0,
1331 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1332 __func__);
1333 debug_cond(DEBUG_SETUP != 0,
1334 "wLength = %d, setup returned\n",
1335 usb_ctrl->wLength);
1336
1337 dwc2_udc_ep0_set_stall(ep);
1338 dev->ep0state = WAIT_FOR_SETUP;
1339
1340 return;
1341 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1342 usb_ctrl->wLength != 0) {
1343
1344 debug_cond(DEBUG_SETUP != 0,
1345 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1346 __func__, usb_ctrl->wLength);
1347
1348 dwc2_udc_ep0_set_stall(ep);
1349 dev->ep0state = WAIT_FOR_SETUP;
1350
1351 return;
1352 }
1353
1354
1355 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1356 ep->bEndpointAddress |= USB_DIR_IN;
1357 } else {
1358 ep->bEndpointAddress &= ~USB_DIR_IN;
1359 }
1360
1361 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1362 == USB_TYPE_STANDARD;
1363
1364 dev->req_pending = 1;
1365
1366
1367 if (dev->req_std) {
1368 switch (usb_ctrl->bRequest) {
1369 case USB_REQ_SET_ADDRESS:
1370 debug_cond(DEBUG_SETUP != 0,
1371 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1372 __func__, usb_ctrl->wValue);
1373 if (usb_ctrl->bRequestType
1374 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1375 break;
1376
1377 udc_set_address(dev, usb_ctrl->wValue);
1378 return;
1379
1380 case USB_REQ_SET_CONFIGURATION:
1381 debug_cond(DEBUG_SETUP != 0,
1382 "=====================================\n");
1383 debug_cond(DEBUG_SETUP != 0,
1384 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1385 __func__, usb_ctrl->wValue);
1386
1387 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1388 reset_available = 1;
1389
1390 break;
1391
1392 case USB_REQ_GET_DESCRIPTOR:
1393 debug_cond(DEBUG_SETUP != 0,
1394 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1395 __func__);
1396 break;
1397
1398 case USB_REQ_SET_INTERFACE:
1399 debug_cond(DEBUG_SETUP != 0,
1400 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1401 __func__, usb_ctrl->wValue);
1402
1403 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1404 reset_available = 1;
1405
1406 break;
1407
1408 case USB_REQ_GET_CONFIGURATION:
1409 debug_cond(DEBUG_SETUP != 0,
1410 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1411 __func__);
1412 break;
1413
1414 case USB_REQ_GET_STATUS:
1415 if (!dwc2_udc_get_status(dev, usb_ctrl))
1416 return;
1417
1418 break;
1419
1420 case USB_REQ_CLEAR_FEATURE:
1421 ep_num = usb_ctrl->wIndex & 0x7f;
1422
1423 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1424 return;
1425
1426 break;
1427
1428 case USB_REQ_SET_FEATURE:
1429 ep_num = usb_ctrl->wIndex & 0x7f;
1430
1431 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1432 return;
1433
1434 break;
1435
1436 default:
1437 debug_cond(DEBUG_SETUP != 0,
1438 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1439 "happened.\n", __func__, usb_ctrl->bRequest);
1440 break;
1441 }
1442 }
1443
1444
1445 if (likely(dev->driver)) {
1446
1447
1448 debug_cond(DEBUG_SETUP != 0,
1449 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1450 __func__);
1451
1452 spin_unlock(&dev->lock);
1453 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1454 spin_lock(&dev->lock);
1455
1456 if (i < 0) {
1457
1458 dwc2_udc_ep0_set_stall(ep);
1459 dev->ep0state = WAIT_FOR_SETUP;
1460
1461 debug_cond(DEBUG_SETUP != 0,
1462 "\tdev->driver->setup failed (%d),"
1463 " bRequest = %d\n",
1464 i, usb_ctrl->bRequest);
1465
1466
1467 } else if (dev->req_pending) {
1468 dev->req_pending = 0;
1469 debug_cond(DEBUG_SETUP != 0,
1470 "\tdev->req_pending...\n");
1471 }
1472
1473 debug_cond(DEBUG_SETUP != 0,
1474 "\tep0state = %s\n", state_names[dev->ep0state]);
1475
1476 }
1477}
1478
1479
1480
1481
1482static void dwc2_handle_ep0(struct dwc2_udc *dev)
1483{
1484 if (dev->ep0state == WAIT_FOR_SETUP) {
1485 debug_cond(DEBUG_OUT_EP != 0,
1486 "%s: WAIT_FOR_SETUP\n", __func__);
1487 dwc2_ep0_setup(dev);
1488
1489 } else {
1490 debug_cond(DEBUG_OUT_EP != 0,
1491 "%s: strange state!!(state = %s)\n",
1492 __func__, state_names[dev->ep0state]);
1493 }
1494}
1495
1496static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1497{
1498 debug_cond(DEBUG_EP0 != 0,
1499 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1500 if (ep_is_in(ep)) {
1501 dev->ep0state = DATA_STATE_XMIT;
1502 dwc2_ep0_write(dev);
1503
1504 } else {
1505 dev->ep0state = DATA_STATE_RECV;
1506 dwc2_ep0_read(dev);
1507 }
1508}
1509
