1
2
3
4
5
6
7
8
9
10
11
12
13
14
15#include <common.h>
16#include <log.h>
17#include <malloc.h>
18#include <memalign.h>
19#include <video_fb.h>
20#include <linux/delay.h>
21#include <linux/list.h>
22#include <linux/fb.h>
23
24#include <linux/errno.h>
25#include <asm/io.h>
26#include <asm/arch/hardware.h>
27
28#include "videomodes.h"
29#include "da8xx-fb.h"
30
31#if !defined(DA8XX_LCD_CNTL_BASE)
32#define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
33#endif
34
35#define DRIVER_NAME "da8xx_lcdc"
36
37#define LCD_VERSION_1 1
38#define LCD_VERSION_2 2
39
40
41#define LCD_END_OF_FRAME1 (1 << 9)
42#define LCD_END_OF_FRAME0 (1 << 8)
43#define LCD_PL_LOAD_DONE (1 << 6)
44#define LCD_FIFO_UNDERFLOW (1 << 5)
45#define LCD_SYNC_LOST (1 << 2)
46
47
48#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
49#define LCD_DMA_BURST_1 0x0
50#define LCD_DMA_BURST_2 0x1
51#define LCD_DMA_BURST_4 0x2
52#define LCD_DMA_BURST_8 0x3
53#define LCD_DMA_BURST_16 0x4
54#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
55#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
56#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
57#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
58
59#define LCD_V2_TFT_24BPP_MODE (1 << 25)
60#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
61
62
63#define LCD_CLK_DIVISOR(x) ((x) << 8)
64#define LCD_RASTER_MODE 0x01
65
66
67#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
68#define PALETTE_AND_DATA 0x00
69#define PALETTE_ONLY 0x01
70#define DATA_ONLY 0x02
71
72#define LCD_MONO_8BIT_MODE (1 << 9)
73#define LCD_RASTER_ORDER (1 << 8)
74#define LCD_TFT_MODE (1 << 7)
75#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
76#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
77#define LCD_V1_PL_INT_ENA (1 << 4)
78#define LCD_V2_PL_INT_ENA (1 << 6)
79#define LCD_MONOCHROME_MODE (1 << 1)
80#define LCD_RASTER_ENABLE (1 << 0)
81#define LCD_TFT_ALT_ENABLE (1 << 23)
82#define LCD_STN_565_ENABLE (1 << 24)
83#define LCD_V2_DMA_CLK_EN (1 << 2)
84#define LCD_V2_LIDD_CLK_EN (1 << 1)
85#define LCD_V2_CORE_CLK_EN (1 << 0)
86#define LCD_V2_LPP_B10 26
87#define LCD_V2_TFT_24BPP_MODE (1 << 25)
88#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
89
90
91#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
92#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
93#define LCD_SYNC_CTRL (1 << 25)
94#define LCD_SYNC_EDGE (1 << 24)
95#define LCD_INVERT_PIXEL_CLOCK (1 << 22)
96#define LCD_INVERT_LINE_CLOCK (1 << 21)
97#define LCD_INVERT_FRAME_CLOCK (1 << 20)
98
99
100#define LCD_CLK_MAIN_RESET (1 << 3)
101
102struct da8xx_lcd_regs {
103 u32 revid;
104 u32 ctrl;
105 u32 stat;
106 u32 lidd_ctrl;
107 u32 lidd_cs0_conf;
108 u32 lidd_cs0_addr;
109 u32 lidd_cs0_data;
110 u32 lidd_cs1_conf;
111 u32 lidd_cs1_addr;
112 u32 lidd_cs1_data;
113 u32 raster_ctrl;
114 u32 raster_timing_0;
115 u32 raster_timing_1;
116 u32 raster_timing_2;
117 u32 raster_subpanel;
118 u32 reserved;
119 u32 dma_ctrl;
120 u32 dma_frm_buf_base_addr_0;
121 u32 dma_frm_buf_ceiling_addr_0;
122 u32 dma_frm_buf_base_addr_1;
123 u32 dma_frm_buf_ceiling_addr_1;
124 u32 resv1;
125 u32 raw_stat;
126 u32 masked_stat;
127 u32 int_ena_set;
128 u32 int_ena_clr;
129 u32 end_of_int_ind;
130
131 u32 clk_ena;
132 u32 clk_reset;
133};
134
135#define LCD_NUM_BUFFERS 1
136
137#define WSI_TIMEOUT 50
138#define PALETTE_SIZE 256
139#define LEFT_MARGIN 64
140#define RIGHT_MARGIN 64
141#define UPPER_MARGIN 32
142#define LOWER_MARGIN 32
143#define WAIT_FOR_FRAME_DONE true
144#define NO_WAIT_FOR_FRAME_DONE false
145
146#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
147
148static struct da8xx_lcd_regs *da8xx_fb_reg_base;
149
150DECLARE_GLOBAL_DATA_PTR;
151
152
153static GraphicDevice gpanel;
154static const struct da8xx_panel *lcd_panel;
155static struct fb_info *da8xx_fb_info;
156static int bits_x_pixel;
157static unsigned int lcd_revision;
158const struct lcd_ctrl_config *da8xx_lcd_cfg;
159
160static inline unsigned int lcdc_read(u32 *addr)
161{
162 return (unsigned int)readl(addr);
163}
164
165static inline void lcdc_write(unsigned int val, u32 *addr)
166{
167 writel(val, addr);
168}
169
170struct da8xx_fb_par {
171 u32 p_palette_base;
172 unsigned char *v_palette_base;
173 dma_addr_t vram_phys;
174 unsigned long vram_size;
175 void *vram_virt;
176 unsigned int dma_start;
177 unsigned int dma_end;
178 struct clk *lcdc_clk;
179 int irq;
180 unsigned short pseudo_palette[16];
181 unsigned int palette_sz;
182 unsigned int pxl_clk;
183 int blank;
184 int vsync_flag;
185 int vsync_timeout;
186};
187
188
189
190static struct fb_var_screeninfo da8xx_fb_var = {
191 .xoffset = 0,
192 .yoffset = 0,
193 .transp = {0, 0, 0},
194 .nonstd = 0,
195 .activate = 0,
196 .height = -1,
197 .width = -1,
198 .pixclock = 46666,
199 .accel_flags = 0,
200 .left_margin = LEFT_MARGIN,
201 .right_margin = RIGHT_MARGIN,
202 .upper_margin = UPPER_MARGIN,
203 .lower_margin = LOWER_MARGIN,
204 .sync = 0,
205 .vmode = FB_VMODE_NONINTERLACED
206};
207
208static struct fb_fix_screeninfo da8xx_fb_fix = {
209 .id = "DA8xx FB Drv",
210 .type = FB_TYPE_PACKED_PIXELS,
211 .type_aux = 0,
212 .visual = FB_VISUAL_PSEUDOCOLOR,
213 .xpanstep = 0,
214 .ypanstep = 1,
215 .ywrapstep = 0,
216 .accel = FB_ACCEL_NONE
217};
218
219
220static inline void lcd_enable_raster(void)
221{
222 u32 reg;
223
224
225 if (lcd_revision == LCD_VERSION_2)
226 lcdc_write(LCD_CLK_MAIN_RESET,
227 &da8xx_fb_reg_base->clk_reset);
228
229 udelay(1000);
230
231 if (lcd_revision == LCD_VERSION_2)
232 lcdc_write(0,
233 &da8xx_fb_reg_base->clk_reset);
234
235 udelay(1000);
236
237 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
238 if (!(reg & LCD_RASTER_ENABLE))
239 lcdc_write(reg | LCD_RASTER_ENABLE,
240 &da8xx_fb_reg_base->raster_ctrl);
241}
242
243
244static inline void lcd_disable_raster(bool wait_for_frame_done)
245{
246 u32 reg;
247 u32 loop_cnt = 0;
248 u32 stat;
249 u32 i = 0;
250
251 if (wait_for_frame_done)
252 loop_cnt = 5000;
253
254 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
255 if (reg & LCD_RASTER_ENABLE)
256 lcdc_write(reg & ~LCD_RASTER_ENABLE,
257 &da8xx_fb_reg_base->raster_ctrl);
258
259
260 do {
261 if (lcd_revision == LCD_VERSION_1)
262 stat = lcdc_read(&da8xx_fb_reg_base->stat);
263 else
264 stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
265
266 mdelay(1);
267 } while (!(stat & 0x01) && (i++ < loop_cnt));
268
269 if (lcd_revision == LCD_VERSION_1)
270 lcdc_write(stat, &da8xx_fb_reg_base->stat);
271 else
272 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
273
274 if ((loop_cnt != 0) && (i >= loop_cnt)) {
275 printf("LCD Controller timed out\n");
276 return;
277 }
278}
279
280static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
281{
282 u32 start;
283 u32 end;
284 u32 reg_ras;
285 u32 reg_dma;
286 u32 reg_int;
287
288
289 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
290 reg_ras &= ~(3 << 20);
291
292 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
293
294 if (load_mode == LOAD_DATA) {
295 start = par->dma_start;
296 end = par->dma_end;
297
298 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
299 if (lcd_revision == LCD_VERSION_1) {
300 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
301 } else {
302 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
303 LCD_V2_END_OF_FRAME0_INT_ENA |
304 LCD_V2_END_OF_FRAME1_INT_ENA |
305 LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
306 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
307 }
308
309#if (LCD_NUM_BUFFERS == 2)
310 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
311 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
312 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
313 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
314 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
315#else
316 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
317 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
318 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
319 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
320 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
321#endif
322
323 } else if (load_mode == LOAD_PALETTE) {
324 start = par->p_palette_base;
325 end = start + par->palette_sz - 1;
326
327 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
328 if (lcd_revision == LCD_VERSION_1) {
329 reg_ras |= LCD_V1_PL_INT_ENA;
330 } else {
331 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
332 LCD_V2_PL_INT_ENA;
333 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
334 }
335
336 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
337 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
338 }
339
340 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
341 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
342
343
344
345
346
347 lcd_enable_raster();
348}
349
350
351static int lcd_cfg_dma(int burst_size)
352{
353 u32 reg;
354
355 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
356 switch (burst_size) {
357 case 1:
358 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
359 break;
360 case 2:
361 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
362 break;
363 case 4:
364 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
365 break;
366 case 8:
367 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
368 break;
369 case 16:
370 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
371 break;
372 default:
373 return -EINVAL;
374 }
375 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
376
377 return 0;
378}
379
380static void lcd_cfg_ac_bias(int period, int transitions_per_int)
381{
382 u32 reg;
383
384
385 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
386 reg |= LCD_AC_BIAS_FREQUENCY(period) |
387 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
388 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
389}
390
391static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
392 int front_porch)
393{
394 u32 reg;
395
396 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
397 reg |= ((back_porch & 0xff) << 24)
398 | ((front_porch & 0xff) << 16)
399 | ((pulse_width & 0x3f) << 10);
400 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
401}
402
403static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
404 int front_porch)
405{
406 u32 reg;
407
408 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
409 reg |= ((back_porch & 0xff) << 24)
410 | ((front_porch & 0xff) << 16)
411 | ((pulse_width & 0x3f) << 10);
412 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
413}
414
415static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
416{
417 u32 reg;
418 u32 reg_int;
419
420 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
421 LCD_MONO_8BIT_MODE |
422 LCD_MONOCHROME_MODE);
423
424 switch (cfg->p_disp_panel->panel_shade) {
425 case MONOCHROME:
426 reg |= LCD_MONOCHROME_MODE;
427 if (cfg->mono_8bit_mode)
428 reg |= LCD_MONO_8BIT_MODE;
429 break;
430 case COLOR_ACTIVE:
431 reg |= LCD_TFT_MODE;
432 if (cfg->tft_alt_mode)
433 reg |= LCD_TFT_ALT_ENABLE;
434 break;
435
436 case COLOR_PASSIVE:
437 if (cfg->stn_565_mode)
438 reg |= LCD_STN_565_ENABLE;
439 break;
440
441 default:
442 return -EINVAL;
443 }
444
445
446 if (lcd_revision == LCD_VERSION_1) {
447 reg |= LCD_V1_UNDERFLOW_INT_ENA;
448 } else {
449 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
450 LCD_V2_UNDERFLOW_INT_ENA;
451 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
452 }
453
454 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
455
456 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
457
458 if (cfg->sync_ctrl)
459 reg |= LCD_SYNC_CTRL;
460 else
461 reg &= ~LCD_SYNC_CTRL;
462
463 if (cfg->sync_edge)
464 reg |= LCD_SYNC_EDGE;
465 else
466 reg &= ~LCD_SYNC_EDGE;
467
468 if (cfg->invert_line_clock)
469 reg |= LCD_INVERT_LINE_CLOCK;
470 else
471 reg &= ~LCD_INVERT_LINE_CLOCK;
472
473 if (cfg->invert_frm_clock)
474 reg |= LCD_INVERT_FRAME_CLOCK;
475 else
476 reg &= ~LCD_INVERT_FRAME_CLOCK;
477
478 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
479
480 return 0;
481}
482
483static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
484 u32 bpp, u32 raster_order)
485{
486 u32 reg;
487
488
489
490 if (lcd_revision == LCD_VERSION_1) {
491
492
493
494
495 width &= 0x3f0;
496 } else {
497
498
499
500
501 width &= 0x7f0;
502 }
503 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
504 reg &= 0xfffffc00;
505 if (lcd_revision == LCD_VERSION_1) {
506 reg |= ((width >> 4) - 1) << 4;
507 } else {
508 width = (width >> 4) - 1;
509 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
510 }
511 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
512
513
514
515 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
516 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
517 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
518
519
520 if (lcd_revision == LCD_VERSION_2) {
521 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
522 reg |= ((height - 1) & 0x400) << 16;
523 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
524 }
525
526
527 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
528 if (raster_order)
529 reg |= LCD_RASTER_ORDER;
530
531 if (bpp == 24)
532 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
533 else if (bpp == 32)
534 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
535 | LCD_V2_TFT_24BPP_UNPACK);
536
537 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
538
539 switch (bpp) {
540 case 1:
541 case 2:
542 case 4:
543 case 16:
544 case 24:
545 case 32:
546 par->palette_sz = 16 * 2;
547 break;
548
549 case 8:
550 par->palette_sz = 256 * 2;
551 break;
552
553 default:
554 return -EINVAL;
555 }
556
557 return 0;
558}
559
560static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
561 unsigned blue, unsigned transp,
562 struct fb_info *info)
563{
564 struct da8xx_fb_par *par = info->par;
565 unsigned short *palette = (unsigned short *) par->v_palette_base;
566 u_short pal;
567 int update_hw = 0;
568
569 if (regno > 255)
570 return 1;
571
572 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
573 return 1;
574
575 if (info->var.bits_per_pixel == 8) {
576 red >>= 4;
577 green >>= 8;
578 blue >>= 12;
579
580 pal = (red & 0x0f00);
581 pal |= (green & 0x00f0);
582 pal |= (blue & 0x000f);
583
584 if (palette[regno] != pal) {
585 update_hw = 1;
586 palette[regno] = pal;
587 }
588 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
589 red >>= (16 - info->var.red.length);
590 red <<= info->var.red.offset;
591
592 green >>= (16 - info->var.green.length);
593 green <<= info->var.green.offset;
594
595 blue >>= (16 - info->var.blue.length);
596 blue <<= info->var.blue.offset;
597
598 par->pseudo_palette[regno] = red | green | blue;
599
600 if (palette[0] != 0x4000) {
601 update_hw = 1;
602 palette[0] = 0x4000;
603 }
604 } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
605 ((info->var.bits_per_pixel == 24) && regno < 24)) {
606 red >>= (24 - info->var.red.length);
607 red <<= info->var.red.offset;
608
609 green >>= (24 - info->var.green.length);
610 green <<= info->var.green.offset;
611
612 blue >>= (24 - info->var.blue.length);
613 blue <<= info->var.blue.offset;
614
615 par->pseudo_palette[regno] = red | green | blue;
616
617 if (palette[0] != 0x4000) {
618 update_hw = 1;
619 palette[0] = 0x4000;
620 }
621 }
622
623
624 if (update_hw)
625 lcd_blit(LOAD_PALETTE, par);
626
627 return 0;
628}
629
630static void lcd_reset(struct da8xx_fb_par *par)
631{
632
633 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
634
635
636 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
637 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
638
639 if (lcd_revision == LCD_VERSION_2) {
640 lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
641
642 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
643 lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
644 }
645}
646
647static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
648{
649 unsigned int lcd_clk, div;
650
651
652 lcd_clk = clk_get(2);
653
654 div = lcd_clk / par->pxl_clk;
655 debug("LCD Clock: %d Divider: %d PixClk: %d\n",
656 lcd_clk, div, par->pxl_clk);
657
658
659 lcdc_write(LCD_CLK_DIVISOR(div) |
660 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
661
662 if (lcd_revision == LCD_VERSION_2)
663 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
664 LCD_V2_CORE_CLK_EN,
665 &da8xx_fb_reg_base->clk_ena);
666}
667
668static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
669 const struct da8xx_panel *panel)
670{
671 u32 bpp;
672 int ret = 0;
673
674 lcd_reset(par);
675
676
677 lcd_calc_clk_divider(par);
678
679 if (panel->invert_pxl_clk)
680 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
681 LCD_INVERT_PIXEL_CLOCK),
682 &da8xx_fb_reg_base->raster_timing_2);
683 else
684 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
685 ~LCD_INVERT_PIXEL_CLOCK),
686 &da8xx_fb_reg_base->raster_timing_2);
687
688
689 ret = lcd_cfg_dma(cfg->dma_burst_sz);
690 if (ret < 0)
691 return ret;
692
693
694 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
695
696
697 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
698 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
699
700
701 ret = lcd_cfg_display(cfg);
702 if (ret < 0)
703 return ret;
704
705 if ((QVGA != cfg->p_disp_panel->panel_type) &&
706 (WVGA != cfg->p_disp_panel->panel_type))
707 return -EINVAL;
708
709 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
710 cfg->bpp >= cfg->p_disp_panel->min_bpp)
711 bpp = cfg->bpp;
712 else
713 bpp = cfg->p_disp_panel->max_bpp;
714 if (bpp == 12)
715 bpp = 16;
716 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
717 (unsigned int)panel->height, bpp,
718 cfg->raster_order);
719 if (ret < 0)
720 return ret;
721
722
723 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
724 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
725
726 return 0;
727}
728
729static void lcdc_dma_start(void)
730{
731 struct da8xx_fb_par *par = da8xx_fb_info->par;
732 lcdc_write(par->dma_start,
733 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
734 lcdc_write(par->dma_end,
735 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
736 lcdc_write(0,
737 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
738 lcdc_write(0,
739 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
740}
741
742static u32 lcdc_irq_handler_rev01(void)
743{
744 struct da8xx_fb_par *par = da8xx_fb_info->par;
745 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
746 u32 reg_ras;
747
748 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
749 debug("LCD_SYNC_LOST\n");
750 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
751 lcdc_write(stat, &da8xx_fb_reg_base->stat);
752 lcd_enable_raster();
753 return LCD_SYNC_LOST;
754 } else if (stat & LCD_PL_LOAD_DONE) {
755 debug("LCD_PL_LOAD_DONE\n");
756
757
758
759
760
761
762 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
763
764 lcdc_write(stat, &da8xx_fb_reg_base->stat);
765
766
767 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
768 reg_ras &= ~LCD_V1_PL_INT_ENA;
769 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
770
771
772 lcd_blit(LOAD_DATA, par);
773 return LCD_PL_LOAD_DONE;
774 } else {
775 lcdc_write(stat, &da8xx_fb_reg_base->stat);
776
777 if (stat & LCD_END_OF_FRAME0)
778 debug("LCD_END_OF_FRAME0\n");
779
780 lcdc_write(par->dma_start,
781 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
782 lcdc_write(par->dma_end,
783 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
784 par->vsync_flag = 1;
785 return LCD_END_OF_FRAME0;
786 }
787 return stat;
788}
789
790static u32 lcdc_irq_handler_rev02(void)
791{
792 struct da8xx_fb_par *par = da8xx_fb_info->par;
793 u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
794 u32 reg_int;
795
796 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
797 debug("LCD_SYNC_LOST\n");
798 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
799 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
800 lcd_enable_raster();
801 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
802 return LCD_SYNC_LOST;
803 } else if (stat & LCD_PL_LOAD_DONE) {
804 debug("LCD_PL_LOAD_DONE\n");
805
806
807
808
809
810
811 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
812
813 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
814
815
816 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
817 (LCD_V2_PL_INT_ENA);
818 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
819
820
821 lcd_blit(LOAD_DATA, par);
822 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
823 return LCD_PL_LOAD_DONE;
824 } else {
825 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
826
827 if (stat & LCD_END_OF_FRAME0)
828 debug("LCD_END_OF_FRAME0\n");
829
830 lcdc_write(par->dma_start,
831 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
832 lcdc_write(par->dma_end,
833 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
834 par->vsync_flag = 1;
835 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
836 return LCD_END_OF_FRAME0;
837 }
838 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
839 return stat;
840}
841
842static u32 lcdc_irq_handler(void)
843{
844 if (lcd_revision == LCD_VERSION_1)
845 return lcdc_irq_handler_rev01();
846 else
847 return lcdc_irq_handler_rev02();
848}
849
850static u32 wait_for_event(u32 event)
851{
852 u32 timeout = 50000;
853 u32 ret;
854
855 do {
856 ret = lcdc_irq_handler();
857 udelay(1000);
858 --timeout;
859 } while (!(ret & event) && timeout);
860
861 if (!(ret & event)) {
862 printf("%s: event %d not hit\n", __func__, event);
863 return -1;
864 }
865
866 return 0;
867
868}
869
870void *video_hw_init(void)
871{
872 struct da8xx_fb_par *par;
873 u32 size;
874 u32 rev;
875 char *p;
876
877 if (!lcd_panel) {
878 printf("Display not initialized\n");
879 return NULL;
880 }
881 gpanel.winSizeX = lcd_panel->width;
882 gpanel.winSizeY = lcd_panel->height;
883 gpanel.plnSizeX = lcd_panel->width;
884 gpanel.plnSizeY = lcd_panel->height;
885
886 switch (bits_x_pixel) {
887 case 32:
888 gpanel.gdfBytesPP = 4;
889 gpanel.gdfIndex = GDF_32BIT_X888RGB;
890 break;
891 case 24:
892 gpanel.gdfBytesPP = 4;
893 gpanel.gdfIndex = GDF_32BIT_X888RGB;
894 break;
895 case 16:
896 gpanel.gdfBytesPP = 2;
897 gpanel.gdfIndex = GDF_16BIT_565RGB;
898 break;
899 default:
900 gpanel.gdfBytesPP = 1;
901 gpanel.gdfIndex = GDF__8BIT_INDEX;
902 break;
903 }
904
905 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
906
907
908 rev = lcdc_read(&da8xx_fb_reg_base->revid);
909 switch (rev) {
910 case 0x4C100102:
911 lcd_revision = LCD_VERSION_1;
912 break;
913 case 0x4F200800:
914 case 0x4F201000:
915 lcd_revision = LCD_VERSION_2;
916 break;
917 default:
918 printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
919 rev);
920 lcd_revision = LCD_VERSION_1;
921 break;
922 }
923
924 debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
925 gpanel.winSizeX,
926 gpanel.winSizeY,
927 da8xx_lcd_cfg->bpp);
928
929 size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
930 da8xx_fb_info = malloc_cache_aligned(size);
931 debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
932
933 if (!da8xx_fb_info) {
934 printf("Memory allocation failed for fb_info\n");
935 return NULL;
936 }
937 memset(da8xx_fb_info, 0, size);
938 p = (char *)da8xx_fb_info;
939 da8xx_fb_info->par = p + sizeof(struct fb_info);
940 debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
941
942 par = da8xx_fb_info->par;
943 par->pxl_clk = lcd_panel->pxl_clk;
944
945 if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
946 printf("lcd_init failed\n");
947 goto err_release_fb;
948 }
949
950
951 par->vram_size = lcd_panel->width * lcd_panel->height *
952 da8xx_lcd_cfg->bpp;
953 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
954
955 par->vram_virt = malloc_cache_aligned(par->vram_size);
956
957 par->vram_phys = (dma_addr_t) par->vram_virt;
958 debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
959 (unsigned int)par->vram_size,
960 (unsigned int)par->vram_virt);
961 if (!par->vram_virt) {
962 printf("GLCD: malloc for frame buffer failed\n");
963 goto err_release_fb;
964 }
965 gd->fb_base = (int)par->vram_virt;
966
967 gpanel.frameAdrs = (unsigned int)par->vram_virt;
968 da8xx_fb_info->screen_base = (char *) par->vram_virt;
969 da8xx_fb_fix.smem_start = gpanel.frameAdrs;
970 da8xx_fb_fix.smem_len = par->vram_size;
971 da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
972
973 par->dma_start = par->vram_phys;
974 par->dma_end = par->dma_start + lcd_panel->height *
975 da8xx_fb_fix.line_length - 1;
976
977
978 par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE);
979 if (!par->v_palette_base) {
980 printf("GLCD: malloc for palette buffer failed\n");
981 goto err_release_fb_mem;
982 }
983 memset(par->v_palette_base, 0, PALETTE_SIZE);
984 par->p_palette_base = (unsigned int)par->v_palette_base;
985
986
987 da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
988
989 da8xx_fb_var.xres = lcd_panel->width;
990 da8xx_fb_var.xres_virtual = lcd_panel->width;
991
992 da8xx_fb_var.yres = lcd_panel->height;
993 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
994
995 da8xx_fb_var.grayscale =
996 da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
997 da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
998
999 da8xx_fb_var.hsync_len = lcd_panel->hsw;
1000 da8xx_fb_var.vsync_len = lcd_panel->vsw;
1001
1002
1003 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1004 da8xx_fb_info->fix = da8xx_fb_fix;
1005 da8xx_fb_info->var = da8xx_fb_var;
1006 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1007 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1008 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1009
1010
1011 memset((void *)par->vram_virt, 0, par->vram_size);
1012 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
1013 if (lcd_revision == LCD_VERSION_1)
1014 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
1015 else
1016 lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
1017 debug("Palette at 0x%x size %d\n", par->p_palette_base,
1018 par->palette_sz);
1019 lcdc_dma_start();
1020
1021
1022 fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
1023
1024
1025 wait_for_event(LCD_PL_LOAD_DONE);
1026
1027
1028 wait_for_event(LCD_END_OF_FRAME0);
1029
1030 return (void *)&gpanel;
1031
1032err_release_fb_mem:
1033 free(par->vram_virt);
1034
1035err_release_fb:
1036 free(da8xx_fb_info);
1037
1038 return NULL;
1039}
1040
1041void da8xx_video_init(const struct da8xx_panel *panel,
1042 const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
1043{
1044 lcd_panel = panel;
1045 da8xx_lcd_cfg = lcd_cfg;
1046 bits_x_pixel = bits_pixel;
1047}
1048
