1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF5475 board. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M5475EVB_H 14#define _M5475EVB_H 15 16/* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21#define CONFIG_MCFUART 22#define CONFIG_SYS_UART_PORT (0) 23 24#undef CONFIG_HW_WATCHDOG 25#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 26 27#define CONFIG_SLTTMR 28 29#ifdef CONFIG_FSLDMAFEC 30# define CONFIG_MII_INIT 1 31# define CONFIG_HAS_ETH1 32# define CONFIG_SYS_DMA_USE_INTSRAM 1 33# define CONFIG_SYS_DISCOVER_PHY 34# define CONFIG_SYS_RX_ETH_BUFFER 32 35# define CONFIG_SYS_TX_ETH_BUFFER 48 36# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 37/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 38# ifndef CONFIG_SYS_DISCOVER_PHY 39# define FECDUPLEX FULL 40# define FECSPEED _100BASET 41# else 42# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 43# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 44# endif 45# endif /* CONFIG_SYS_DISCOVER_PHY */ 46 47# define CONFIG_IPADDR 192.162.1.2 48# define CONFIG_NETMASK 255.255.255.0 49# define CONFIG_SERVERIP 192.162.1.1 50# define CONFIG_GATEWAYIP 192.162.1.1 51#endif 52 53#ifdef CONFIG_CMD_USB 54# define CONFIG_USB_OHCI_NEW 55 56# define CONFIG_PCI_OHCI 57 58# undef CONFIG_SYS_USB_OHCI_BOARD_INIT 59# undef CONFIG_SYS_USB_OHCI_CPU_INIT 60# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 61# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 62# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 63#endif 64 65/* I2C */ 66#define CONFIG_SYS_I2C 67#define CONFIG_SYS_I2C_FSL 68#define CONFIG_SYS_FSL_I2C_SPEED 80000 69#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 70#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 71#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 72 73/* PCI */ 74#ifdef CONFIG_CMD_PCI 75#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 76 77#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 78 79#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 80#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 81#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 82 83#define CONFIG_SYS_PCI_IO_BUS 0x71000000 84#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 85#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 86 87#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 88#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 89#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 90#endif 91 92#define CONFIG_UDP_CHECKSUM 93 94#ifdef CONFIG_MCFFEC 95# define CONFIG_IPADDR 192.162.1.2 96# define CONFIG_NETMASK 255.255.255.0 97# define CONFIG_SERVERIP 192.162.1.1 98# define CONFIG_GATEWAYIP 192.162.1.1 99#endif /* FEC_ENET */ 100 101#define CONFIG_HOSTNAME "M547xEVB" 102#define CONFIG_EXTRA_ENV_SETTINGS \ 103 "netdev=eth0\0" \ 104 "loadaddr=10000\0" \ 105 "u-boot=u-boot.bin\0" \ 106 "load=tftp ${loadaddr) ${u-boot}\0" \ 107 "upd=run load; run prog\0" \ 108 "prog=prot off bank 1;" \ 109 "era ff800000 ff83ffff;" \ 110 "cp.b ${loadaddr} ff800000 ${filesize};"\ 111 "save\0" \ 112 "" 113 114#define CONFIG_PRAM 512 /* 512 KB */ 115 116#define CONFIG_SYS_LOAD_ADDR 0x00010000 117 118#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 119#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 120 121#define CONFIG_SYS_MBAR 0xF0000000 122#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 123#define CONFIG_SYS_INTSRAMSZ 0x8000 124 125/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 126 127/* 128 * Low Level Configuration Settings 129 * (address mappings, register initial values, etc.) 130 * You should know what you are doing if you make changes here. 131 */ 132/*----------------------------------------------------------------------- 133 * Definitions for initial stack pointer and data area (in DPRAM) 134 */ 135#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 136#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 137#define CONFIG_SYS_INIT_RAM_CTRL 0x21 138#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 139#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 140#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 141#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 142#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 143 144/*----------------------------------------------------------------------- 145 * Start addresses for the final memory configuration 146 * (Set up by the startup code) 147 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 148 */ 149#define CONFIG_SYS_SDRAM_BASE 0x00000000 150#define CONFIG_SYS_SDRAM_CFG1 0x73711630 151#define CONFIG_SYS_SDRAM_CFG2 0x46770000 152#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 153#define CONFIG_SYS_SDRAM_EMOD 0x40010000 154#define CONFIG_SYS_SDRAM_MODE 0x018D0000 155#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 156#ifdef CONFIG_SYS_DRAMSZ1 157# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 158#else 159# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 160#endif 161 162#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 163#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 164 165#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 166 167/* Reserve 256 kB for malloc() */ 168#define CONFIG_SYS_MALLOC_LEN (256 << 10) 169/* 170 * For booting Linux, the board info and command line data 171 * have to be in the first 8 MB of memory, since this is 172 * the maximum mapped by the Linux kernel during initialization ?? 173 */ 174#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 175 176/*----------------------------------------------------------------------- 177 * FLASH organization 178 */ 179#ifdef CONFIG_SYS_FLASH_CFI 180# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 181# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 182# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 183#ifdef CONFIG_SYS_NOR1SZ 184# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 185# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 186# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 187#else 188# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 189# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 190#endif 191#endif 192 193/* Configuration for environment 194 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 195 * First time runing may have env crc error warning if there is 196 * no correct environment on the flash. 197 */ 198 199/*----------------------------------------------------------------------- 200 * Cache Configuration 201 */ 202#define CONFIG_SYS_CACHELINE_SIZE 16 203 204#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 205 CONFIG_SYS_INIT_RAM_SIZE - 8) 206#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 207 CONFIG_SYS_INIT_RAM_SIZE - 4) 208#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 209 CF_CACR_IDCM) 210#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 211#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 212 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 213 CF_ACR_EN | CF_ACR_SM_ALL) 214#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 215 CF_CACR_IEC | CF_CACR_ICINVA) 216#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 217 CF_CACR_DEC | CF_CACR_DDCM_P | \ 218 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 219 220/*----------------------------------------------------------------------- 221 * Chipselect bank definitions 222 */ 223/* 224 * CS0 - NOR Flash 1, 2, 4, or 8MB 225 * CS1 - NOR Flash 226 * CS2 - Available 227 * CS3 - Available 228 * CS4 - Available 229 * CS5 - Available 230 */ 231#define CONFIG_SYS_CS0_BASE 0xFF800000 232#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 233#define CONFIG_SYS_CS0_CTRL 0x00101980 234 235#ifdef CONFIG_SYS_NOR1SZ 236#define CONFIG_SYS_CS1_BASE 0xE0000000 237#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 238#define CONFIG_SYS_CS1_CTRL 0x00101D80 239#endif 240 241#endif /* _M5475EVB_H */ 242