LXR uboot/include/configs/ds414.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   4 */
   5
   6#ifndef _CONFIG_SYNOLOGY_DS414_H
   7#define _CONFIG_SYNOLOGY_DS414_H
   8
   9/*
  10 * High Level Configuration Options (easy to change)
  11 */
  12
  13/*
  14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  15 * for DDR ECC byte filling in the SPL before loading the main
  16 * U-Boot into it.
  17 */
  18#define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  19
  20/* I2C */
  21#define CONFIG_SYS_I2C
  22#define CONFIG_SYS_I2C_MVTWSI
  23#define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  24#define CONFIG_SYS_I2C_SLAVE            0x0
  25#define CONFIG_SYS_I2C_SPEED            100000
  26
  27/* Environment in SPI NOR flash */
  28
  29#define CONFIG_SYS_NETA_INTERFACE_TYPE  PHY_INTERFACE_MODE_RGMII
  30
  31/* PCIe support */
  32#ifndef CONFIG_SPL_BUILD
  33#define CONFIG_PCI_SCAN_SHOW
  34#endif
  35
  36/* USB/EHCI/XHCI configuration */
  37
  38#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  39
  40/* FIXME: broken XHCI support
  41 * Below defines should enable support for the two rear USB3 ports. Sadly, this
  42 * does not work because:
  43 * - xhci-pci seems to not support DM_USB, so with that enabled it is not
  44 *   found.
  45 * - USB init fails, controller does not respond in time */
  46
  47#if !defined(CONFIG_USB_XHCI_HCD)
  48#define CONFIG_EHCI_IS_TDI
  49#endif
  50
  51/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
  52
  53/*
  54 * mv-common.h should be defined after CMD configs since it used them
  55 * to enable certain macros
  56 */
  57#include "mv-common.h"
  58
  59/*
  60 * Memory layout while starting into the bin_hdr via the
  61 * BootROM:
  62 *
  63 * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
  64 * 0x4000.4030                  bin_hdr start address
  65 * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
  66 * 0x4007.fffc                  BootROM stack top
  67 *
  68 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  69 * L2 cache thus cannot be used.
  70 */
  71
  72/* SPL */
  73/* Defines for SPL */
  74#define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
  75
  76#define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
  77#define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
  78
  79#ifdef CONFIG_SPL_BUILD
  80#define CONFIG_SYS_MALLOC_SIMPLE
  81#endif
  82
  83#define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
  84#define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
  85
  86#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
  87/* SPL related SPI defines */
  88#define CONFIG_SYS_U_BOOT_OFFS          CONFIG_SYS_SPI_U_BOOT_OFFS
  89#endif
  90
  91/* DS414 bus width is 32bits */
  92#define CONFIG_DDR_32BIT
  93
  94/* Default Environment */
  95#define CONFIG_BOOTCOMMAND      "sf read ${loadaddr} 0xd0000 0x700000; bootm"
  96#define CONFIG_LOADADDR         0x80000
  97
  98#endif /* _CONFIG_SYNOLOGY_DS414_H */
  99