1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuration settings for the Espresso7420 board. 4 * Copyright (C) 2016 Samsung Electronics 5 * Thomas Abraham <thomas.ab@samsung.com> 6 */ 7 8#ifndef __CONFIG_EXYNOS7420_COMMON_H 9#define __CONFIG_EXYNOS7420_COMMON_H 10 11/* High Level Configuration Options */ 12#define CONFIG_SAMSUNG /* in a SAMSUNG core */ 13#define CONFIG_EXYNOS7420 /* Exynos7 Family */ 14#define CONFIG_S5P 15 16#include <asm/arch/cpu.h> /* get chip and board defs */ 17#include <linux/sizes.h> 18 19/* Size of malloc() pool before and after relocation */ 20#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) 21 22/* Miscellaneous configurable options */ 23#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 24#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ 25 26/* Boot Argument Buffer Size */ 27#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 28 29/* select serial console configuration */ 30 31/* Timer input clock frequency */ 32#define COUNTER_FREQUENCY 24000000 33 34/* Device Tree */ 35#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420" 36 37/* IRAM Layout */ 38#define CONFIG_IRAM_BASE 0x02100000 39#define CONFIG_IRAM_SIZE 0x58000 40#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) 41#define CPU_RELEASE_ADDR secondary_boot_addr 42 43/* select serial console configuration */ 44 45#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 46 47#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 48#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 49#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 50#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 51#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 52#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 53#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 54#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 55#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 56#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 57#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 58#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 59#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 60#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 61#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 62#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 63 64/* Configuration of ENV Blocks */ 65 66#define BOOT_TARGET_DEVICES(func) \ 67 func(MMC, mmc, 1) \ 68 func(MMC, mmc, 0) \ 69 70#ifndef MEM_LAYOUT_ENV_SETTINGS 71#define MEM_LAYOUT_ENV_SETTINGS \ 72 "bootm_size=0x10000000\0" \ 73 "kernel_addr_r=0x42000000\0" \ 74 "fdt_addr_r=0x43000000\0" \ 75 "ramdisk_addr_r=0x43300000\0" \ 76 "scriptaddr=0x50000000\0" \ 77 "pxefile_addr_r=0x51000000\0" 78#endif 79 80#ifndef EXYNOS_DEVICE_SETTINGS 81#define EXYNOS_DEVICE_SETTINGS \ 82 "stdin=serial\0" \ 83 "stdout=serial\0" \ 84 "stderr=serial\0" 85#endif 86 87#ifndef EXYNOS_FDTFILE_SETTING 88#define EXYNOS_FDTFILE_SETTING 89#endif 90 91#define CONFIG_EXTRA_ENV_SETTINGS \ 92 EXYNOS_DEVICE_SETTINGS \ 93 EXYNOS_FDTFILE_SETTING \ 94 MEM_LAYOUT_ENV_SETTINGS 95 96#endif /* __CONFIG_EXYNOS7420_COMMON_H */ 97