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10#ifndef _DDR_DEFS_H
11#define _DDR_DEFS_H
12
13#include <asm/arch/hardware.h>
14#include <asm/emif.h>
15
16
17#define VTP_CTRL_READY (0x1 << 5)
18#define VTP_CTRL_ENABLE (0x1 << 6)
19#define VTP_CTRL_START_EN (0x1)
20#ifdef CONFIG_AM43XX
21#define DDR_CKE_CTRL_NORMAL 0x3
22#else
23#define DDR_CKE_CTRL_NORMAL 0x1
24#endif
25#define PHY_EN_DYN_PWRDN (0x1 << 20)
26
27
28#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
29#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
30#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
31#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
32#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
33#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
34#define MT47H128M16RT25E_RATIO 0x80
35#define MT47H128M16RT25E_RD_DQS 0x12
36#define MT47H128M16RT25E_PHY_WR_DATA 0x40
37#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
38#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
39
40
41#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
42#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
43#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
44#define MT41J128MJT125_EMIF_TIM3 0x501F830F
45#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
46#define MT41J128MJT125_EMIF_SDREF 0x0000093B
47#define MT41J128MJT125_ZQ_CFG 0x50074BE4
48#define MT41J128MJT125_RATIO 0x40
49#define MT41J128MJT125_INVERT_CLKOUT 0x1
50#define MT41J128MJT125_RD_DQS 0x3B
51#define MT41J128MJT125_WR_DQS 0x85
52#define MT41J128MJT125_PHY_WR_DATA 0xC1
53#define MT41J128MJT125_PHY_FIFO_WE 0x100
54#define MT41J128MJT125_IOCTRL_VALUE 0x18B
55
56
57#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
58#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
59#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
60#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
61#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
62#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
63#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
64#define MT41J128MJT125_RATIO_400MHz 0x80
65#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
66#define MT41J128MJT125_RD_DQS_400MHz 0x3A
67#define MT41J128MJT125_WR_DQS_400MHz 0x3B
68#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
69#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
70
71
72#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
73#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
74#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
75#define MT41K128MJT187E_EMIF_TIM3 0x501F830F
76#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
77#define MT41K128MJT187E_EMIF_SDREF 0x0000093B
78#define MT41K128MJT187E_ZQ_CFG 0x50074BE4
79#define MT41K128MJT187E_RATIO 0x40
80#define MT41K128MJT187E_INVERT_CLKOUT 0x1
81#define MT41K128MJT187E_RD_DQS 0x3B
82#define MT41K128MJT187E_WR_DQS 0x85
83#define MT41K128MJT187E_PHY_WR_DATA 0xC1
84#define MT41K128MJT187E_PHY_FIFO_WE 0x100
85#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
86
87
88#define MT41K128M16JT125K_EMIF_READ_LATENCY 0x07
89#define MT41K128M16JT125K_EMIF_TIM1 0x0AAAD4DB
90#define MT41K128M16JT125K_EMIF_TIM2 0x2A437FDA
91#define MT41K128M16JT125K_EMIF_TIM3 0x501F83FF
92#define MT41K128M16JT125K_EMIF_SDCFG 0x61A052B2
93#define MT41K128M16JT125K_EMIF_SDREF 0x00000C30
94#define MT41K128M16JT125K_ZQ_CFG 0x50074BE4
95#define MT41K128M16JT125K_RATIO 0x80
96#define MT41K128M16JT125K_INVERT_CLKOUT 0x0
97#define MT41K128M16JT125K_RD_DQS 0x38
98#define MT41K128M16JT125K_WR_DQS 0x46
99#define MT41K128M16JT125K_PHY_WR_DATA 0x7D
100#define MT41K128M16JT125K_PHY_FIFO_WE 0x9B
101#define MT41K128M16JT125K_IOCTRL_VALUE 0x18B
102
103
104#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
105
106
107#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
108
109
110#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
111#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
112#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
113#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
114#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
115#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
116#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
117#define MT41J256M8HX15E_RATIO 0x40
118#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
119#define MT41J256M8HX15E_RD_DQS 0x3B
120#define MT41J256M8HX15E_WR_DQS 0x85
121#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
122#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
123#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
124
125
126#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
127#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
128#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
129#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
130#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
131#define MT41K256M16HA125E_EMIF_SDREF 0xC30
132#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
133#define MT41K256M16HA125E_RATIO 0x80
134#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
135#define MT41K256M16HA125E_RD_DQS 0x38
136#define MT41K256M16HA125E_WR_DQS 0x44
137#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
138#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
139#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
140
141
142#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
143#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
144#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
145#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
146#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
147#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
148#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
149#define MT41J512M8RH125_RATIO 0x80
150#define MT41J512M8RH125_INVERT_CLKOUT 0x0
151#define MT41J512M8RH125_RD_DQS 0x3B
152#define MT41J512M8RH125_WR_DQS 0x3C
153#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
154#define MT41J512M8RH125_PHY_WR_DATA 0x74
155#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
156
157
158#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
159#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
160#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
161#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
162#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
163#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
164#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
165#define K4B2G1646EBIH9_RATIO 0x80
166#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
167#define K4B2G1646EBIH9_RD_DQS 0x35
168#define K4B2G1646EBIH9_WR_DQS 0x3A
169#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
170#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
171#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
172
173#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
174#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
175#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
176#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
177#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
178#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
179#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
180
181#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
182#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
183#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
184#define DDR3_DATA0_IOCTRL_VALUE 0x84
185#define DDR3_DATA1_IOCTRL_VALUE 0x84
186#define DDR3_DATA2_IOCTRL_VALUE 0x84
187#define DDR3_DATA3_IOCTRL_VALUE 0x84
188
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191
192void config_dmm(const struct dmm_lisa_map_regs *regs);
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197void config_sdram(const struct emif_regs *regs, int nr);
198void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
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203void set_sdram_timings(const struct emif_regs *regs, int nr);
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208void config_ddr_phy(const struct emif_regs *regs, int nr);
209
210struct ddr_cmd_regs {
211 unsigned int resv0[7];
212 unsigned int cm0csratio;
213 unsigned int resv1[3];
214 unsigned int cm0iclkout;
215 unsigned int resv2[8];
216 unsigned int cm1csratio;
217 unsigned int resv3[3];
218 unsigned int cm1iclkout;
219 unsigned int resv4[8];
220 unsigned int cm2csratio;
221 unsigned int resv5[3];
222 unsigned int cm2iclkout;
223 unsigned int resv6[3];
224};
225
226struct ddr_data_regs {
227 unsigned int dt0rdsratio0;
228 unsigned int resv1[4];
229 unsigned int dt0wdsratio0;
230 unsigned int resv2[4];
231 unsigned int dt0wiratio0;
232 unsigned int resv3;
233 unsigned int dt0wimode0;
234 unsigned int dt0giratio0;
235 unsigned int resv4;
236 unsigned int dt0gimode0;
237 unsigned int dt0fwsratio0;
238 unsigned int resv5[4];
239 unsigned int dt0dqoffset;
240 unsigned int dt0wrsratio0;
241 unsigned int resv6[4];
242 unsigned int dt0rdelays0;
243 unsigned int dt0dldiff0;
244 unsigned int resv7[12];
245};
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250
251
252struct ddr_regs {
253 unsigned int resv0[3];
254 unsigned int cm0config;
255 unsigned int cm0configclk;
256 unsigned int resv1[2];
257 unsigned int cm0csratio;
258 unsigned int resv2[3];
259 unsigned int cm0iclkout;
260 unsigned int resv3[4];
261 unsigned int cm1config;
262 unsigned int cm1configclk;
263 unsigned int resv4[2];
264 unsigned int cm1csratio;
265 unsigned int resv5[3];
266 unsigned int cm1iclkout;
267 unsigned int resv6[4];
268 unsigned int cm2config;
269 unsigned int cm2configclk;
270 unsigned int resv7[2];
271 unsigned int cm2csratio;
272 unsigned int resv8[3];
273 unsigned int cm2iclkout;
274 unsigned int resv9[12];
275 unsigned int dt0rdsratio0;
276 unsigned int resv10[4];
277 unsigned int dt0wdsratio0;
278 unsigned int resv11[4];
279 unsigned int dt0wiratio0;
280 unsigned int resv12;
281 unsigned int dt0wimode0;
282 unsigned int dt0giratio0;
283 unsigned int resv13;
284 unsigned int dt0gimode0;
285 unsigned int dt0fwsratio0;
286 unsigned int resv14[4];
287 unsigned int dt0dqoffset;
288 unsigned int dt0wrsratio0;
289 unsigned int resv15[4];
290 unsigned int dt0rdelays0;
291 unsigned int dt0dldiff0;
292};
293
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295
296
297struct cmd_control {
298 unsigned long cmd0csratio;
299 unsigned long cmd0csforce;
300 unsigned long cmd0csdelay;
301 unsigned long cmd0iclkout;
302 unsigned long cmd1csratio;
303 unsigned long cmd1csforce;
304 unsigned long cmd1csdelay;
305 unsigned long cmd1iclkout;
306 unsigned long cmd2csratio;
307 unsigned long cmd2csforce;
308 unsigned long cmd2csdelay;
309 unsigned long cmd2iclkout;
310};
311
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313
314
315struct ddr_data {
316 unsigned long datardsratio0;
317 unsigned long datawdsratio0;
318 unsigned long datawiratio0;
319 unsigned long datagiratio0;
320 unsigned long datafwsratio0;
321 unsigned long datawrsratio0;
322};
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326
327void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
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330
331
332void config_ddr_data(const struct ddr_data *data, int nr);
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335
336
337struct ddr_cmdtctrl {
338 unsigned int cm0ioctl;
339 unsigned int cm1ioctl;
340 unsigned int cm2ioctl;
341 unsigned int resv2[12];
342 unsigned int dt0ioctl;
343 unsigned int dt1ioctl;
344 unsigned int dt2ioctrl;
345 unsigned int dt3ioctrl;
346 unsigned int resv3[4];
347 unsigned int emif_sdram_config_ext;
348};
349
350struct ctrl_ioregs {
351 unsigned int cm0ioctl;
352 unsigned int cm1ioctl;
353 unsigned int cm2ioctl;
354 unsigned int dt0ioctl;
355 unsigned int dt1ioctl;
356 unsigned int dt2ioctrl;
357 unsigned int dt3ioctrl;
358 unsigned int emif_sdram_config_ext;
359};
360
361
362
363
364void config_io_ctrl(const struct ctrl_ioregs *ioregs);
365
366struct ddr_ctrl {
367 unsigned int ddrioctrl;
368 unsigned int resv1[325];
369 unsigned int ddrckectrl;
370};
371
372#ifdef CONFIG_TI816X
373void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
374 const struct emif_regs *regs,
375 const struct dmm_lisa_map_regs *lisa_regs, int nrs);
376#else
377void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
378 const struct ddr_data *data, const struct cmd_control *ctrl,
379 const struct emif_regs *regs, int nr);
380#endif
381void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
382
383#endif
384