LXR uboot/arch/arm/include/asm/arch-fsl-layerscape/fsl

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2018 NXP
   4 * Copyright 2015 Freescale Semiconductor, Inc.
   5 */
   6
   7#ifndef __FSL_SERDES_H__
   8#define __FSL_SERDES_H__
   9
  10#include <config.h>
  11
  12#ifdef CONFIG_FSL_LSCH3
  13enum srds_prtcl {
  14        /*
  15         * Nobody will check whether the device 'NONE' has been configured,
  16         * So use it to indicate if the serdes_prtcl_map has been initialized.
  17         */
  18        NONE = 0,
  19        PCIE1,
  20        PCIE2,
  21        PCIE3,
  22        PCIE4,
  23        PCIE5,
  24        PCIE6,
  25        SATA1,
  26        SATA2,
  27        SATA3,
  28        SATA4,
  29        XAUI1,
  30        XAUI2,
  31        XFI1,
  32        XFI2,
  33        XFI3,
  34        XFI4,
  35        XFI5,
  36        XFI6,
  37        XFI7,
  38        XFI8,
  39        XFI9,
  40        XFI10,
  41        XFI11,
  42        XFI12,
  43        XFI13,
  44        XFI14,
  45        SGMII1,
  46        SGMII2,
  47        SGMII3,
  48        SGMII4,
  49        SGMII5,
  50        SGMII6,
  51        SGMII7,
  52        SGMII8,
  53        SGMII9,
  54        SGMII10,
  55        SGMII11,
  56        SGMII12,
  57        SGMII13,
  58        SGMII14,
  59        SGMII15,
  60        SGMII16,
  61        SGMII17,
  62        SGMII18,
  63        QSGMII_A,
  64        QSGMII_B,
  65        QSGMII_C,
  66        QSGMII_D,
  67        SGMII_T1,
  68        SGMII_T2,
  69        SGMII_T3,
  70        SGMII_T4,
  71        SXGMII1,
  72        SXGMII2,
  73        SXGMII3,
  74        SXGMII4,
  75        QXGMII1,
  76        QXGMII2,
  77        QXGMII3,
  78        QXGMII4,
  79        _25GE1,
  80        _25GE2,
  81        _25GE3,
  82        _25GE4,
  83        _25GE5,
  84        _25GE6,
  85        _25GE7,
  86        _25GE8,
  87        _25GE9,
  88        _25GE10,
  89        _40GE1,
  90        _40GE2,
  91        _50GE1,
  92        _50GE2,
  93        _100GE1,
  94        _100GE2,
  95        SERDES_PRCTL_COUNT
  96};
  97
  98enum srds {
  99        FSL_SRDS_1  = 0,
 100        FSL_SRDS_2  = 1,
 101        NXP_SRDS_3  = 2,
 102};
 103#elif defined(CONFIG_FSL_LSCH2)
 104enum srds_prtcl {
 105        /*
 106         * Nobody will check whether the device 'NONE' has been configured,
 107         * So use it to indicate if the serdes_prtcl_map has been initialized.
 108         */
 109        NONE = 0,
 110        PCIE1,
 111        PCIE2,
 112        PCIE3,
 113        PCIE4,
 114        SATA1,
 115        SATA2,
 116        SRIO1,
 117        SRIO2,
 118        SGMII_FM1_DTSEC1,
 119        SGMII_FM1_DTSEC2,
 120        SGMII_FM1_DTSEC3,
 121        SGMII_FM1_DTSEC4,
 122        SGMII_FM1_DTSEC5,
 123        SGMII_FM1_DTSEC6,
 124        SGMII_FM1_DTSEC9,
 125        SGMII_FM1_DTSEC10,
 126        SGMII_FM2_DTSEC1,
 127        SGMII_FM2_DTSEC2,
 128        SGMII_FM2_DTSEC3,
 129        SGMII_FM2_DTSEC4,
 130        SGMII_FM2_DTSEC5,
 131        SGMII_FM2_DTSEC6,
 132        SGMII_FM2_DTSEC9,
 133        SGMII_FM2_DTSEC10,
 134        SGMII_TSEC1,
 135        SGMII_TSEC2,
 136        SGMII_TSEC3,
 137        SGMII_TSEC4,
 138        XAUI_FM1,
 139        XAUI_FM2,
 140        AURORA,
 141        CPRI1,
 142        CPRI2,
 143        CPRI3,
 144        CPRI4,
 145        CPRI5,
 146        CPRI6,
 147        CPRI7,
 148        CPRI8,
 149        XAUI_FM1_MAC9,
 150        XAUI_FM1_MAC10,
 151        XAUI_FM2_MAC9,
 152        XAUI_FM2_MAC10,
 153        HIGIG_FM1_MAC9,
 154        HIGIG_FM1_MAC10,
 155        HIGIG_FM2_MAC9,
 156        HIGIG_FM2_MAC10,
 157        QSGMII_FM1_A,           /* A indicates MACs 1,2,5,6 */
 158        QSGMII_FM1_B,           /* B indicates MACs 5,6,9,10 */
 159        QSGMII_FM2_A,
 160        QSGMII_FM2_B,
 161        XFI_FM1_MAC1,
 162        XFI_FM1_MAC2,
 163        XFI_FM1_MAC9,
 164        XFI_FM1_MAC10,
 165        XFI_FM2_MAC9,
 166        XFI_FM2_MAC10,
 167        INTERLAKEN,
 168        QSGMII_SW1_A,           /* Indicates ports on L2 Switch */
 169        QSGMII_SW1_B,
 170        SGMII_2500_FM1_DTSEC1,
 171        SGMII_2500_FM1_DTSEC2,
 172        SGMII_2500_FM1_DTSEC3,
 173        SGMII_2500_FM1_DTSEC4,
 174        SGMII_2500_FM1_DTSEC5,
 175        SGMII_2500_FM1_DTSEC6,
 176        SGMII_2500_FM1_DTSEC9,
 177        SGMII_2500_FM1_DTSEC10,
 178        SGMII_2500_FM2_DTSEC1,
 179        SGMII_2500_FM2_DTSEC2,
 180        SGMII_2500_FM2_DTSEC3,
 181        SGMII_2500_FM2_DTSEC4,
 182        SGMII_2500_FM2_DTSEC5,
 183        SGMII_2500_FM2_DTSEC6,
 184        SGMII_2500_FM2_DTSEC9,
 185        SGMII_2500_FM2_DTSEC10,
 186        TX_CLK,
 187        SERDES_PRCTL_COUNT
 188};
 189
 190enum srds {
 191        FSL_SRDS_1  = 0,
 192        FSL_SRDS_2  = 1,
 193};
 194
 195#endif
 196
 197int is_serdes_configured(enum srds_prtcl device);
 198void fsl_serdes_init(void);
 199int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
 200enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
 201int is_serdes_prtcl_valid(int serdes, u32 prtcl);
 202int serdes_get_number(int serdes, int cfg);
 203void fsl_rgmii_init(void);
 204
 205#ifdef CONFIG_FSL_LSCH2
 206const char *serdes_clock_to_string(u32 clock);
 207int get_serdes_protocol(void);
 208#endif
 209#ifdef CONFIG_SYS_HAS_SERDES
 210/* Get the volt of SVDD in unit mV */
 211int get_serdes_volt(void);
 212/* Set the volt of SVDD in unit mV */
 213int set_serdes_volt(int svdd);
 214/* The target volt of SVDD in unit mV */
 215int setup_serdes_volt(u32 svdd);
 216#endif
 217
 218#endif /* __FSL_SERDES_H__ */
 219