uboot/arch/arm/include/asm/arch-omap4/sys_proto.h
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   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2010
   4 * Texas Instruments, <www.ti.com>
   5 */
   6
   7#ifndef _SYS_PROTO_H_
   8#define _SYS_PROTO_H_
   9
  10#include <asm/arch/omap.h>
  11#include <asm/arch/clock.h>
  12#include <asm/io.h>
  13#include <asm/omap_common.h>
  14#include <linux/mtd/omap_gpmc.h>
  15#include <asm/arch/mux_omap4.h>
  16#include <asm/ti-common/sys_proto.h>
  17
  18#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  19extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
  20extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
  21extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
  22extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
  23extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2;
  24extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2;
  25extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2;
  26#else
  27extern const struct lpddr2_device_details elpida_2G_S4_details;
  28extern const struct lpddr2_device_details elpida_4G_S4_details;
  29#endif
  30
  31#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
  32extern const struct lpddr2_device_timings jedec_default_timings;
  33#else
  34extern const struct lpddr2_device_timings elpida_2G_S4_timings;
  35#endif
  36
  37struct omap_sysinfo {
  38        char *board_string;
  39};
  40extern const struct omap_sysinfo sysinfo;
  41
  42void gpmc_init(void);
  43void watchdog_init(void);
  44u32 get_device_type(void);
  45void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
  46void set_muxconf_regs(void);
  47u32 wait_on_value(u32, u32, void *, u32);
  48void sdelay(unsigned long);
  49void setup_early_clocks(void);
  50void prcm_init(void);
  51void do_board_detect(void);
  52void bypass_dpll(u32 const base);
  53void freq_update_core(void);
  54u32 get_sys_clk_freq(void);
  55u32 omap4_ddr_clk(void);
  56void cancel_out(u32 *num, u32 *den, u32 den_limit);
  57void sdram_init(void);
  58u32 omap_sdram_size(void);
  59u32 cortex_rev(void);
  60void save_omap_boot_params(void);
  61void init_omap_revision(void);
  62void do_io_settings(void);
  63void sri2c_init(void);
  64int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
  65u32 warm_reset(void);
  66void force_emif_self_refresh(void);
  67void setup_warmreset_time(void);
  68
  69#define OMAP4_SERVICE_PL310_CONTROL_REG_SET     0x102
  70
  71#endif
  72