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5#ifndef _ASM_ARCH_SDRAM_RK322X_H
6#define _ASM_ARCH_SDRAM_RK322X_H
7
8#ifndef __ASSEMBLY__
9#include <linux/bitops.h>
10#endif
11
12struct rk322x_sdram_channel {
13
14
15
16
17
18 u8 rank;
19 u8 col;
20 u8 bk;
21 u8 bw;
22 u8 dbw;
23 u8 row_3_4;
24 u8 cs0_row;
25 u8 cs1_row;
26#if CONFIG_IS_ENABLED(OF_PLATDATA)
27
28
29
30
31
32
33
34 u8 dummy;
35#endif
36};
37
38struct rk322x_ddr_pctl {
39 u32 scfg;
40 u32 sctl;
41 u32 stat;
42 u32 intrstat;
43 u32 reserved0[(0x40 - 0x10) / 4];
44 u32 mcmd;
45 u32 powctl;
46 u32 powstat;
47 u32 cmdtstat;
48 u32 cmdtstaten;
49 u32 reserved1[(0x60 - 0x54) / 4];
50 u32 mrrcfg0;
51 u32 mrrstat0;
52 u32 mrrstat1;
53 u32 reserved2[(0x7c - 0x6c) / 4];
54
55 u32 mcfg1;
56 u32 mcfg;
57 u32 ppcfg;
58 u32 mstat;
59 u32 lpddr2zqcfg;
60 u32 reserved3;
61
62 u32 dtupdes;
63 u32 dtuna;
64 u32 dtune;
65 u32 dtuprd0;
66 u32 dtuprd1;
67 u32 dtuprd2;
68 u32 dtuprd3;
69 u32 dtuawdt;
70 u32 reserved4[(0xc0 - 0xb4) / 4];
71
72 u32 togcnt1u;
73 u32 tinit;
74 u32 trsth;
75 u32 togcnt100n;
76 u32 trefi;
77 u32 tmrd;
78 u32 trfc;
79 u32 trp;
80 u32 trtw;
81 u32 tal;
82 u32 tcl;
83 u32 tcwl;
84 u32 tras;
85 u32 trc;
86 u32 trcd;
87 u32 trrd;
88 u32 trtp;
89 u32 twr;
90 u32 twtr;
91 u32 texsr;
92 u32 txp;
93 u32 txpdll;
94 u32 tzqcs;
95 u32 tzqcsi;
96 u32 tdqs;
97 u32 tcksre;
98 u32 tcksrx;
99 u32 tcke;
100 u32 tmod;
101 u32 trstl;
102 u32 tzqcl;
103 u32 tmrr;
104 u32 tckesr;
105 u32 tdpd;
106 u32 tref_mem_ddr3;
107 u32 reserved5[(0x180 - 0x14c) / 4];
108 u32 ecccfg;
109 u32 ecctst;
110 u32 eccclr;
111 u32 ecclog;
112 u32 reserved6[(0x200 - 0x190) / 4];
113 u32 dtuwactl;
114 u32 dturactl;
115 u32 dtucfg;
116 u32 dtuectl;
117 u32 dtuwd0;
118 u32 dtuwd1;
119 u32 dtuwd2;
120 u32 dtuwd3;
121 u32 dtuwdm;
122 u32 dturd0;
123 u32 dturd1;
124 u32 dturd2;
125 u32 dturd3;
126 u32 dtulfsrwd;
127 u32 dtulfsrrd;
128 u32 dtueaf;
129
130 u32 dfitctrldelay;
131 u32 dfiodtcfg;
132 u32 dfiodtcfg1;
133 u32 dfiodtrankmap;
134
135 u32 dfitphywrdata;
136 u32 dfitphywrlat;
137 u32 reserved7[(0x260 - 0x258) / 4];
138 u32 dfitrddataen;
139 u32 dfitphyrdlat;
140 u32 reserved8[(0x270 - 0x268) / 4];
141 u32 dfitphyupdtype0;
142 u32 dfitphyupdtype1;
143 u32 dfitphyupdtype2;
144 u32 dfitphyupdtype3;
145 u32 dfitctrlupdmin;
146 u32 dfitctrlupdmax;
147 u32 dfitctrlupddly;
148 u32 reserved9;
149 u32 dfiupdcfg;
150 u32 dfitrefmski;
151 u32 dfitctrlupdi;
152 u32 reserved10[(0x2ac - 0x29c) / 4];
153 u32 dfitrcfg0;
154 u32 dfitrstat0;
155 u32 dfitrwrlvlen;
156 u32 dfitrrdlvlen;
157 u32 dfitrrdlvlgateen;
158 u32 dfiststat0;
159 u32 dfistcfg0;
160 u32 dfistcfg1;
161 u32 reserved11;
162 u32 dfitdramclken;
163 u32 dfitdramclkdis;
164 u32 dfistcfg2;
165 u32 dfistparclr;
166 u32 dfistparlog;
167 u32 reserved12[(0x2f0 - 0x2e4) / 4];
168
169 u32 dfilpcfg0;
170 u32 reserved13[(0x300 - 0x2f4) / 4];
171 u32 dfitrwrlvlresp0;
172 u32 dfitrwrlvlresp1;
173 u32 dfitrwrlvlresp2;
174 u32 dfitrrdlvlresp0;
175 u32 dfitrrdlvlresp1;
176 u32 dfitrrdlvlresp2;
177 u32 dfitrwrlvldelay0;
178 u32 dfitrwrlvldelay1;
179 u32 dfitrwrlvldelay2;
180 u32 dfitrrdlvldelay0;
181 u32 dfitrrdlvldelay1;
182 u32 dfitrrdlvldelay2;
183 u32 dfitrrdlvlgatedelay0;
184 u32 dfitrrdlvlgatedelay1;
185 u32 dfitrrdlvlgatedelay2;
186 u32 dfitrcmd;
187 u32 reserved14[(0x3f8 - 0x340) / 4];
188 u32 ipvr;
189 u32 iptr;
190};
191check_member(rk322x_ddr_pctl, iptr, 0x03fc);
192
193struct rk322x_ddr_phy {
194 u32 ddrphy_reg[0x100];
195};
196
197struct rk322x_pctl_timing {
198 u32 togcnt1u;
199 u32 tinit;
200 u32 trsth;
201 u32 togcnt100n;
202 u32 trefi;
203 u32 tmrd;
204 u32 trfc;
205 u32 trp;
206 u32 trtw;
207 u32 tal;
208 u32 tcl;
209 u32 tcwl;
210 u32 tras;
211 u32 trc;
212 u32 trcd;
213 u32 trrd;
214 u32 trtp;
215 u32 twr;
216 u32 twtr;
217 u32 texsr;
218 u32 txp;
219 u32 txpdll;
220 u32 tzqcs;
221 u32 tzqcsi;
222 u32 tdqs;
223 u32 tcksre;
224 u32 tcksrx;
225 u32 tcke;
226 u32 tmod;
227 u32 trstl;
228 u32 tzqcl;
229 u32 tmrr;
230 u32 tckesr;
231 u32 tdpd;
232 u32 trefi_mem_ddr3;
233};
234
235struct rk322x_phy_timing {
236 u32 mr[4];
237 u32 mr11;
238 u32 bl;
239 u32 cl_al;
240};
241
242struct rk322x_msch_timings {
243 u32 ddrtiming;
244 u32 ddrmode;
245 u32 readlatency;
246 u32 activate;
247 u32 devtodev;
248};
249
250struct rk322x_service_sys {
251 u32 id_coreid;
252 u32 id_revisionid;
253 u32 ddrconf;
254 u32 ddrtiming;
255 u32 ddrmode;
256 u32 readlatency;
257 u32 activate;
258 u32 devtodev;
259};
260
261struct rk322x_base_params {
262 struct rk322x_msch_timings noc_timing;
263 u32 ddrconfig;
264 u32 ddr_freq;
265 u32 dramtype;
266
267
268
269 u32 stride;
270 u32 odt;
271};
272
273
274#define DFI_INIT_START BIT(0)
275#define DFI_DATA_BYTE_DISABLE_EN BIT(2)
276
277
278#define DFI_DRAM_CLK_SR_EN BIT(0)
279#define DFI_DRAM_CLK_DPD_EN BIT(1)
280
281
282#define DFI_PARITY_INTR_EN BIT(0)
283#define DFI_PARITY_EN BIT(1)
284
285
286#define TLP_RESP_TIME_SHIFT 16
287#define LP_SR_EN BIT(8)
288#define LP_PD_EN BIT(0)
289
290
291#define TCTRL_DELAY_TIME_SHIFT 0
292
293
294#define TPHY_WRDATA_TIME_SHIFT 0
295
296
297#define TPHY_RDLAT_TIME_SHIFT 0
298
299
300#define TDRAM_CLK_DIS_TIME_SHIFT 0
301
302
303#define TDRAM_CLK_EN_TIME_SHIFT 0
304
305
306#define RANK0_ODT_WRITE_SEL BIT(3)
307#define RANK1_ODT_WRITE_SEL BIT(11)
308
309
310#define ODT_LEN_BL8_W_SHIFT 16
311
312
313#define ACDLLCR_DLLDIS BIT(31)
314#define ACDLLCR_DLLSRST BIT(30)
315
316
317#define DXDLLCR_DLLDIS BIT(31)
318#define DXDLLCR_DLLSRST BIT(30)
319
320
321#define DLLGCR_SBIAS BIT(30)
322
323
324#define DQSRTT BIT(9)
325#define DQRTT BIT(10)
326
327
328#define PIR_INIT BIT(0)
329#define PIR_DLLSRST BIT(1)
330#define PIR_DLLLOCK BIT(2)
331#define PIR_ZCAL BIT(3)
332#define PIR_ITMSRST BIT(4)
333#define PIR_DRAMRST BIT(5)
334#define PIR_DRAMINIT BIT(6)
335#define PIR_QSTRN BIT(7)
336#define PIR_RVTRN BIT(8)
337#define PIR_ICPC BIT(16)
338#define PIR_DLLBYP BIT(17)
339#define PIR_CTLDINIT BIT(18)
340#define PIR_CLRSR BIT(28)
341#define PIR_LOCKBYP BIT(29)
342#define PIR_ZCALBYP BIT(30)
343#define PIR_INITBYP BIT(31)
344
345
346#define PGCR_DFTLMT_SHIFT 3
347#define PGCR_DFTCMP_SHIFT 2
348#define PGCR_DQSCFG_SHIFT 1
349#define PGCR_ITMDMD_SHIFT 0
350
351
352#define PGSR_IDONE BIT(0)
353#define PGSR_DLDONE BIT(1)
354#define PGSR_ZCDONE BIT(2)
355#define PGSR_DIDONE BIT(3)
356#define PGSR_DTDONE BIT(4)
357#define PGSR_DTERR BIT(5)
358#define PGSR_DTIERR BIT(6)
359#define PGSR_DFTERR BIT(7)
360#define PGSR_RVERR BIT(8)
361#define PGSR_RVEIRR BIT(9)
362
363
364#define PRT_ITMSRST_SHIFT 18
365#define PRT_DLLLOCK_SHIFT 6
366#define PRT_DLLSRST_SHIFT 0
367
368
369#define PRT_DINIT0_SHIFT 0
370#define PRT_DINIT1_SHIFT 19
371
372
373#define PRT_DINIT2_SHIFT 0
374#define PRT_DINIT3_SHIFT 17
375
376
377#define DDRMD_LPDDR 0
378#define DDRMD_DDR 1
379#define DDRMD_DDR2 2
380#define DDRMD_DDR3 3
381#define DDRMD_LPDDR2_LPDDR3 4
382#define DDRMD_MASK 7
383#define DDRMD_SHIFT 0
384#define PDQ_MASK 7
385#define PDQ_SHIFT 4
386
387
388#define DQSNRES_MASK 0xf
389#define DQSNRES_SHIFT 8
390#define DQSRES_MASK 0xf
391#define DQSRES_SHIFT 4
392
393
394#define TDQSCKMAX_SHIFT 27
395#define TDQSCKMAX_MASK 7
396#define TDQSCK_SHIFT 24
397#define TDQSCK_MASK 7
398
399
400#define DQSGX_SHIFT 5
401#define DQSGX_MASK 7
402#define DQSGE_SHIFT 8
403#define DQSGE_MASK 7
404
405
406#define INIT_STATE 0
407#define CFG_STATE 1
408#define GO_STATE 2
409#define SLEEP_STATE 3
410#define WAKEUP_STATE 4
411
412
413#define LP_TRIG_SHIFT 4
414#define LP_TRIG_MASK 7
415#define PCTL_STAT_MASK 7
416#define INIT_MEM 0
417#define CONFIG 1
418#define CONFIG_REQ 2
419#define ACCESS 3
420#define ACCESS_REQ 4
421#define LOW_POWER 5
422#define LOW_POWER_ENTRY_REQ 6
423#define LOW_POWER_EXIT_REQ 7
424
425
426#define PD_OUTPUT_SHIFT 0
427#define PU_OUTPUT_SHIFT 5
428#define PD_ONDIE_SHIFT 10
429#define PU_ONDIE_SHIFT 15
430#define ZDEN_SHIFT 28
431
432
433#define SBIAS_BYPASS BIT(23)
434
435
436#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
437#define PD_IDLE_SHIFT 8
438#define MDDR_EN (2 << 22)
439#define LPDDR2_EN (3 << 22)
440#define LPDDR3_EN (1 << 22)
441#define DDR2_EN (0 << 5)
442#define DDR3_EN (1 << 5)
443#define LPDDR2_S2 (0 << 6)
444#define LPDDR2_S4 (1 << 6)
445#define MDDR_LPDDR2_BL_2 (0 << 20)
446#define MDDR_LPDDR2_BL_4 (1 << 20)
447#define MDDR_LPDDR2_BL_8 (2 << 20)
448#define MDDR_LPDDR2_BL_16 (3 << 20)
449#define DDR2_DDR3_BL_4 0
450#define DDR2_DDR3_BL_8 1
451#define TFAW_SHIFT 18
452#define PD_EXIT_SLOW (0 << 17)
453#define PD_EXIT_FAST (1 << 17)
454#define PD_TYPE_SHIFT 16
455#define BURSTLENGTH_SHIFT 20
456
457
458#define POWER_UP_START BIT(0)
459
460
461#define POWER_UP_DONE BIT(0)
462
463
464enum {
465 DESELECT_CMD = 0,
466 PREA_CMD,
467 REF_CMD,
468 MRS_CMD,
469 ZQCS_CMD,
470 ZQCL_CMD,
471 RSTL_CMD,
472 MRR_CMD = 8,
473 DPDE_CMD,
474};
475
476#define BANK_ADDR_MASK 7
477#define BANK_ADDR_SHIFT 17
478#define CMD_ADDR_MASK 0x1fff
479#define CMD_ADDR_SHIFT 4
480
481#define LPDDR23_MA_SHIFT 4
482#define LPDDR23_MA_MASK 0xff
483#define LPDDR23_OP_SHIFT 12
484#define LPDDR23_OP_MASK 0xff
485
486#define START_CMD (1u << 31)
487
488
489enum {
490
491 SOFT_RESET_MASK = 3,
492 SOFT_DERESET_ANALOG = 1 << 2,
493 SOFT_DERESET_DIGITAL = 1 << 3,
494 SOFT_RESET_SHIFT = 2,
495
496
497 PHY_DDR3 = 0,
498 PHY_DDR2 = 1,
499 PHY_LPDDR3 = 2,
500 PHY_LPDDR2 = 3,
501
502 PHT_BL_8 = 1 << 2,
503 PHY_BL_4 = 0 << 2,
504
505
506 MEMORY_SELECT_DDR3 = 0 << 0,
507 MEMORY_SELECT_LPDDR3 = 2 << 0,
508 MEMORY_SELECT_LPDDR2 = 3 << 0,
509 DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4,
510 DQS_SQU_CAL_SEL_CS1 = 1 << 4,
511 DQS_SQU_CAL_SEL_CS0 = 2 << 4,
512 DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
513 DQS_SQU_CAL_BYPASS_MODE = 1 << 1,
514 DQS_SQU_CAL_START = 1 << 0,
515 DQS_SQU_NO_CAL = 0 << 0,
516};
517
518
519enum {
520 PHY_RON_RTT_DISABLE = 0,
521 PHY_RON_RTT_451OHM = 1,
522 PHY_RON_RTT_225OHM,
523 PHY_RON_RTT_150OHM,
524 PHY_RON_RTT_112OHM,
525 PHY_RON_RTT_90OHM,
526 PHY_RON_RTT_75OHM,
527 PHY_RON_RTT_64OHM = 7,
528
529 PHY_RON_RTT_56OHM = 16,
530 PHY_RON_RTT_50OHM,
531 PHY_RON_RTT_45OHM,
532 PHY_RON_RTT_41OHM,
533 PHY_RON_RTT_37OHM,
534 PHY_RON_RTT_34OHM,
535 PHY_RON_RTT_33OHM,
536 PHY_RON_RTT_30OHM = 23,
537
538 PHY_RON_RTT_28OHM = 24,
539 PHY_RON_RTT_26OHM,
540 PHY_RON_RTT_25OHM,
541 PHY_RON_RTT_23OHM,
542 PHY_RON_RTT_22OHM,
543 PHY_RON_RTT_21OHM,
544 PHY_RON_RTT_20OHM,
545 PHY_RON_RTT_19OHM = 31,
546};
547
548
549enum {
550 DQS_DLL_NO_DELAY = 0,
551 DQS_DLL_22P5_DELAY,
552 DQS_DLL_45_DELAY,
553 DQS_DLL_67P5_DELAY,
554 DQS_DLL_90_DELAY,
555 DQS_DLL_112P5_DELAY,
556 DQS_DLL_135_DELAY,
557 DQS_DLL_157P5_DELAY,
558};
559
560
561#define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0))
562#define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0))
563#define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7))
564#define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7))
565
566#define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8))
567#define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8))
568
569#define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6))
570#define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6))
571
572#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n))
573#define DDR3_DLL_RESET (1 << 8)
574
575#endif
576
