1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2013 Atmel Corporation 4 * Bo Shen <voice.shen@atmel.com> 5 * 6 * Copyright (C) 2015 Atmel Corporation 7 * Wenyou Yang <wenyou.yang@atmel.com> 8 */ 9 10#ifndef __ATMEL_MPDDRC_H__ 11#define __ATMEL_MPDDRC_H__ 12 13struct atmel_mpddrc_config { 14 u32 mr; 15 u32 rtr; 16 u32 cr; 17 u32 tpr0; 18 u32 tpr1; 19 u32 tpr2; 20 u32 md; 21 u32 lpddr23_lpr; 22 u32 cal_mr4; 23 u32 tim_cal; 24}; 25 26/* 27 * Only define the needed register in mpddr 28 * If other register needed, will add them later 29 */ 30struct atmel_mpddr { 31 u32 mr; /* 0x00: Mode Register */ 32 u32 rtr; /* 0x04: Refresh Timer Register */ 33 u32 cr; /* 0x08: Configuration Register */ 34 u32 tpr0; /* 0x0c: Timing Parameter 0 Register */ 35 u32 tpr1; /* 0x10: Timing Parameter 1 Register */ 36 u32 tpr2; /* 0x14: Timing Parameter 2 Register */ 37 u32 reserved; /* 0x18: Reserved */ 38 u32 lpr; /* 0x1c: Low-power Register */ 39 u32 md; /* 0x20: Memory Device Register */ 40 u32 reserved1; /* 0x24: Reserved */ 41 u32 lpddr23_lpr; /* 0x28: LPDDR2-LPDDR3 Low-power Register*/ 42 u32 cal_mr4; /* 0x2c: Calibration and MR4 Register */ 43 u32 tim_cal; /* 0x30: Timing Calibration Register */ 44 u32 io_calibr; /* 0x34: IO Calibration */ 45 u32 ocms; /* 0x38: OCMS Register */ 46 u32 ocms_key1; /* 0x3c: OCMS KEY1 Register */ 47 u32 ocms_key2; /* 0x40: OCMS KEY2 Register */ 48 u32 conf_arbiter; /* 0x44: Configuration Arbiter Register */ 49 u32 timeout; /* 0x48: Timeout Port 0/1/2/3 Register */ 50 u32 req_port0123; /* 0x4c: Request Port 0/1/2/3 Register */ 51 u32 req_port4567; /* 0x50: Request Port 4/5/6/7 Register */ 52 u32 bdw_port0123; /* 0x54: Bandwidth Port 0/1/2/3 Register */ 53 u32 bdw_port4567; /* 0x58: Bandwidth Port 4/5/6/7 Register */ 54 u32 rd_data_path; /* 0x5c: Read Datapath Register */ 55 u32 reserved2[33]; 56 u32 wpmr; /* 0xe4: Write Protection Mode Register */ 57 u32 wpsr; /* 0xe8: Write Protection Status Register */ 58 u32 reserved3[4]; 59 u32 version; /* 0xfc: IP version */ 60}; 61 62 63int ddr2_init(const unsigned int base, 64 const unsigned int ram_address, 65 const struct atmel_mpddrc_config *mpddr_value); 66 67int lpddr2_init(const unsigned int base, 68 const unsigned int ram_address, 69 const struct atmel_mpddrc_config *mpddr_value); 70 71int ddr3_init(const unsigned int base, 72 const unsigned int ram_address, 73 const struct atmel_mpddrc_config *mpddr_value); 74 75/* Bit field in mode register */ 76#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 77#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 78#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 79#define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 80#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 81#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 82#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 83#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 84#define ATMEL_MPDDRC_MR_MRS(v) (((v) & 0xFF) << 0x8) 85 86/* Bit field in refresh timer register */ 87#define ATMEL_MPDDRC_RTR_ADJ_REF (0x1 << 16) 88#define ATMEL_MPDDRC_RTR_MR4VALUE(v) (((v) & 0x7) << 20) 89 90/* Bit field in configuration register */ 91#define ATMEL_MPDDRC_CR_NC_MASK 0x3 92#define ATMEL_MPDDRC_CR_NC_COL_9 0x0 93#define ATMEL_MPDDRC_CR_NC_COL_10 0x1 94#define ATMEL_MPDDRC_CR_NC_COL_11 0x2 95#define ATMEL_MPDDRC_CR_NC_COL_12 0x3 96#define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) 97#define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) 98#define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) 99#define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) 100#define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) 101#define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) 102#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) 103#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) 104#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) 105#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) 106#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) 107#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) 108#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) 109#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) 110#define ATMEL_MPDDRC_CR_ZQ_INIT (0x0 << 10) 111#define ATMEL_MPDDRC_CR_ZQ_LONG (0x1 << 10) 112#define ATMEL_MPDDRC_CR_ZQ_SHORT (0x2 << 10) 113#define ATMEL_MPDDRC_CR_ZQ_RESET (0x3 << 10) 114#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) 115#define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) 116#define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) 117#define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) 118#define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) 119#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) 120#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) 121 122/* Bit field in timing parameter 0 register */ 123#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 124#define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf 125#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 126#define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf 127#define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 128#define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf 129#define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 130#define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf 131#define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 132#define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf 133#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 134#define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf 135#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 136#define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 137#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 138#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 139#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 140#define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf 141 142/* Bit field in timing parameter 1 register */ 143#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 144#define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f 145#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 146#define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff 147#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 148#define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff 149#define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 150#define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf 151 152/* Bit field in timing parameter 2 register */ 153#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 154#define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf 155#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 156#define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf 157#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 158#define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf 159#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 160#define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 161#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 162#define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf 163 164/* Bit field in Memory Device Register */ 165#define ATMEL_MPDDRC_MD_SDR_SDRAM 0x0 166#define ATMEL_MPDDRC_MD_LP_SDR_SDRAM 0x1 167#define ATMEL_MPDDRC_MD_DDR_SDRAM 0x2 168#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 169#define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4 170#define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5 171#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 172#define ATMEL_MPDDRC_MD_LPDDR2_SDRAM 0x7 173#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) 174#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) 175#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) 176 177/* Bit field in I/O Calibration Register */ 178#define ATMEL_MPDDRC_IO_CALIBR_RDIV 0x7 179 180#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_34_3 0x1 181#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_40 0x2 182#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48 0x3 183#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_60 0x4 184#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_80 0x6 185#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_120 0x7 186 187#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_35 0x2 188#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_43 0x3 189#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 0x4 190#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_70 0x6 191#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_105 0x7 192 193#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2 194#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3 195#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4 196#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6 197#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7 198 199#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2 200#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3 201#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4 202#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6 203#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7 204 205#define ATMEL_MPDDRC_IO_CALIBR_TZQIO (0x7f << 8) 206#define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8) 207 208#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP (0xf << 16) 209#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP_(x) (((x) & 0xf) << 16) 210#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN (0xf << 20) 211#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN_(x) (((x) & 0xf) << 20) 212 213#define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4) 214 215/* Bit field in Read Data Path Register */ 216#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING 0x3 217#define ATMEL_MPDDRC_RD_DATA_PATH_NO_SHIFT 0x0 218#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE 0x1 219#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2 220#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3 221 222/* Bit field in LPDDR2 - LPDDR3 Low Power Register */ 223#define ATMEL_MPDDRC_LPDDR23_LPR_DS(x) (((x) & 0xf) << 24) 224 225/* Bit field in CAL_MR4 Calibration and MR4 Register */ 226#define ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(x) (((x) & 0xffff) << 0) 227#define ATMEL_MPDDRC_CAL_MR4_MR4R(x) (((x) & 0xffff) << 16) 228 229/* Bit field in TIM_CAL Timing Calibration Register */ 230#define ATMEL_MPDDRC_CALR_ZQCS(x) (((x) & 0xff) << 0) 231 232#endif 233