LXR uboot/arch/arm/mach-ipq40xx/clock-ipq4019.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Clock drivers for Qualcomm IPQ40xx
   4 *
   5 * Copyright (c) 2020 Sartura Ltd.
   6 *
   7 * Author: Robert Marko <robert.marko@sartura.hr>
   8 *
   9 */
  10
  11#include <clk-uclass.h>
  12#include <common.h>
  13#include <dm.h>
  14#include <errno.h>
  15
  16#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
  17
  18struct msm_clk_priv {
  19        phys_addr_t base;
  20};
  21
  22ulong msm_set_rate(struct clk *clk, ulong rate)
  23{
  24        switch (clk->id) {
  25        case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
  26                /* This clock is already initialized by SBL1 */
  27                return 0;
  28        default:
  29                return -EINVAL;
  30        }
  31}
  32
  33static int msm_clk_probe(struct udevice *dev)
  34{
  35        struct msm_clk_priv *priv = dev_get_priv(dev);
  36
  37        priv->base = dev_read_addr(dev);
  38        if (priv->base == FDT_ADDR_T_NONE)
  39                return -EINVAL;
  40
  41        return 0;
  42}
  43
  44static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
  45{
  46        return msm_set_rate(clk, rate);
  47}
  48
  49static int msm_enable(struct clk *clk)
  50{
  51        switch (clk->id) {
  52        case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
  53                /* This clock is already initialized by SBL1 */
  54                return 0;
  55        case GCC_PRNG_AHB_CLK: /*PRNG*/
  56                /* This clock is already initialized by SBL1 */
  57                return 0;
  58        case GCC_USB3_MASTER_CLK:
  59        case GCC_USB3_SLEEP_CLK:
  60        case GCC_USB3_MOCK_UTMI_CLK:
  61        case GCC_USB2_MASTER_CLK:
  62        case GCC_USB2_SLEEP_CLK:
  63        case GCC_USB2_MOCK_UTMI_CLK:
  64                /* These clocks is already initialized by SBL1 */
  65                return 0;
  66        default:
  67                return -EINVAL;
  68        }
  69}
  70
  71static struct clk_ops msm_clk_ops = {
  72        .set_rate = msm_clk_set_rate,
  73        .enable = msm_enable,
  74};
  75
  76static const struct udevice_id msm_clk_ids[] = {
  77        { .compatible = "qcom,gcc-ipq4019" },
  78        { }
  79};
  80
  81U_BOOT_DRIVER(clk_msm) = {
  82        .name           = "clk_msm",
  83        .id             = UCLASS_CLK,
  84        .of_match       = msm_clk_ids,
  85        .ops            = &msm_clk_ops,
  86        .priv_auto      = sizeof(struct msm_clk_priv),
  87        .probe          = msm_clk_probe,
  88};
  89