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24#include <common.h>
25#include <init.h>
26#include <asm/global_data.h>
27#include <asm/io.h>
28#include <asm/arch/mem.h>
29#include <asm/arch/sys_proto.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32extern omap3_sysinfo sysinfo;
33
34static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
35
36
37
38
39
40u32 is_mem_sdr(void)
41{
42 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
43 return 1;
44 return 0;
45}
46
47
48
49
50
51
52
53void make_cs1_contiguous(void)
54{
55 u32 size, a_add_low, a_add_high;
56
57 size = get_sdr_cs_size(CS0);
58 size >>= 25;
59 a_add_high = (size & 3) << 8;
60 a_add_low = (size & 0x3C) >> 2;
61 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
62
63}
64
65
66
67
68
69
70u32 get_sdr_cs_size(u32 cs)
71{
72 u32 size;
73
74
75 size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
76 size &= 0x3FF;
77 size <<= 21;
78 return size;
79}
80
81
82
83
84
85u32 get_sdr_cs_offset(u32 cs)
86{
87 u32 offset;
88
89 if (!cs)
90 return 0;
91
92 offset = readl(&sdrc_base->cs_cfg);
93 offset = (offset & 15) << 27 | (offset & 0x300) << 17;
94
95 return offset;
96}
97
98
99
100
101
102
103static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
104 struct board_sdrc_timings *timings)
105{
106
107 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
108 writel(timings->ctrla, &sdrc_actim_base->ctrla);
109 writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
110 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
111 writel(CMD_NOP, &sdrc_base->cs[cs].manual);
112 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
113 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
114 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
115 writel(timings->mr, &sdrc_base->cs[cs].mr);
116
117
118
119
120
121 if (!mem_ok(cs))
122 writel(0, &sdrc_base->cs[cs].mcfg);
123}
124
125
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127
128
129
130
131void do_sdrc_init(u32 cs, u32 early)
132{
133 struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
134 struct board_sdrc_timings timings;
135
136 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
137 sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
138
139
140 timings.sharing = SDRC_SHARING;
141
142
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149
150
151#ifdef CONFIG_SPL_BUILD
152
153 get_board_mem_timings(&timings);
154#endif
155 if (early) {
156
157 writel(SOFTRESET, &sdrc_base->sysconfig);
158 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
159 12000000);
160 writel(0, &sdrc_base->sysconfig);
161
162
163 writel(timings.sharing, &sdrc_base->sharing);
164
165
166 writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
167 &sdrc_base->power);
168
169 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
170 sdelay(0x20000);
171#ifdef CONFIG_SPL_BUILD
172 write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
173 make_cs1_contiguous();
174 write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
175#endif
176
177 }
178
179
180
181
182
183
184
185 if (cs == CS1) {
186 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
187 timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
188 timings.ctrla = readl(&sdrc_actim_base0->ctrla);
189 timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
190 timings.mr = readl(&sdrc_base->cs[CS0].mr);
191 write_sdrc_timings(cs, sdrc_actim_base1, &timings);
192 }
193}
194
195
196
197
198
199int dram_init(void)
200{
201 unsigned int size0 = 0, size1 = 0;
202
203 size0 = get_sdr_cs_size(CS0);
204
205
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209
210
211 make_cs1_contiguous();
212 do_sdrc_init(CS1, NOT_EARLY);
213 size1 = get_sdr_cs_size(CS1);
214
215 gd->ram_size = size0 + size1;
216
217 return 0;
218}
219
220int dram_init_banksize(void)
221{
222 unsigned int size0 = 0, size1 = 0;
223
224 size0 = get_sdr_cs_size(CS0);
225 size1 = get_sdr_cs_size(CS1);
226
227 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
228 gd->bd->bi_dram[0].size = size0;
229 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
230 gd->bd->bi_dram[1].size = size1;
231
232 return 0;
233}
234
235
236
237
238
239
240void mem_init(void)
241{
242
243 do_sdrc_init(CS0, EARLY_INIT);
244}
245