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6#include <common.h>
7#include <log.h>
8#include <asm/io.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/gp_padctrl.h>
11#include <asm/arch/pinmux.h>
12#include <asm/arch/tegra.h>
13#include <asm/arch-tegra/clk_rst.h>
14#include <asm/arch-tegra/pmc.h>
15#include <asm/arch-tegra/scu.h>
16#include <linux/delay.h>
17#include "cpu.h"
18
19int get_num_cpus(void)
20{
21 struct apb_misc_gp_ctlr *gp;
22 uint rev;
23 debug("%s entry\n", __func__);
24
25 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
26 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
27
28 switch (rev) {
29 case CHIPID_TEGRA20:
30 return 2;
31 break;
32 case CHIPID_TEGRA30:
33 case CHIPID_TEGRA114:
34 case CHIPID_TEGRA124:
35 case CHIPID_TEGRA210:
36 default:
37 return 4;
38 break;
39 }
40}
41
42
43
44
45struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
46
47
48
49
50
51
52
53
54
55
56 {
57 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 },
58 { .n = 625, .m = 12, .p = 0, .cpcon = 8 },
59 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 },
60 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 },
61 { .n = 0, .m = 0, .p = 0, .cpcon = 0 },
62 { .n = 0, .m = 0, .p = 0, .cpcon = 0 },
63 },
64
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71
72
73
74 {
75 { .n = 923, .m = 10, .p = 0, .cpcon = 12 },
76 { .n = 750, .m = 12, .p = 0, .cpcon = 8 },
77 { .n = 600, .m = 6, .p = 0, .cpcon = 12 },
78 { .n = 600, .m = 13, .p = 0, .cpcon = 12 },
79 { .n = 0, .m = 0, .p = 0, .cpcon = 0 },
80 { .n = 0, .m = 0, .p = 0, .cpcon = 0 },
81 },
82
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91
92 {
93 { .n = 600, .m = 13, .p = 0, .cpcon = 8 },
94 { .n = 500, .m = 16, .p = 0, .cpcon = 8 },
95 { .n = 600, .m = 12, .p = 0, .cpcon = 8 },
96 { .n = 600, .m = 26, .p = 0, .cpcon = 8 },
97 { .n = 0, .m = 0, .p = 0, .cpcon = 0 },
98 { .n = 0, .m = 0, .p = 0, .cpcon = 0 },
99 },
100
101
102
103
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107
108
109 {
110 { .n = 108, .m = 1, .p = 1 },
111 { .n = 73, .m = 1, .p = 1 },
112 { .n = 116, .m = 1, .p = 1 },
113 { .n = 108, .m = 2, .p = 1 },
114 { .n = 0, .m = 0, .p = 0 },
115 { .n = 0, .m = 0, .p = 0 },
116 },
117
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126
127 {
128 { .n = 108, .m = 1, .p = 1 },
129 { .n = 73, .m = 1, .p = 1 },
130 { .n = 116, .m = 1, .p = 1 },
131 { .n = 108, .m = 2, .p = 1 },
132 { .n = 0, .m = 0, .p = 0 },
133 { .n = 0, .m = 0, .p = 0 },
134 },
135
136
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144
145 {
146 { .n = 108, .m = 1, .p = 1 },
147 { .n = 73, .m = 1, .p = 1 },
148 { .n = 116, .m = 1, .p = 1 },
149 { .n = 108, .m = 2, .p = 1 },
150 { .n = 36, .m = 1, .p = 1 },
151 { .n = 58, .m = 2, .p = 1 },
152 },
153};
154
155static inline void pllx_set_iddq(void)
156{
157#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
158 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
159 u32 reg;
160 debug("%s entry\n", __func__);
161
162
163 reg = readl(&clkrst->crc_pllx_misc3);
164 reg &= ~PLLX_IDDQ_MASK;
165 writel(reg, &clkrst->crc_pllx_misc3);
166 udelay(2);
167 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
168 readl(&clkrst->crc_pllx_misc3));
169#endif
170}
171
172int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
173 u32 divp, u32 cpcon)
174{
175 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
176 int chip = tegra_get_chip();
177 u32 reg;
178 debug("%s entry\n", __func__);
179
180
181 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
182 debug("%s: PLLX already enabled, returning\n", __func__);
183 return 0;
184 }
185
186 pllx_set_iddq();
187
188
189 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
190 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
191 writel(reg, &pll->pll_base);
192
193
194 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
195 reg = (cpcon << pllinfo->kcp_shift);
196 else
197 reg = 0;
198
199
200
201
202
203
204 if (divn > 600)
205 reg |= (1 << PLL_DCCON_SHIFT);
206 writel(reg, &pll->pll_misc);
207
208
209 reg = readl(&pll->pll_base);
210 reg &= ~PLL_BYPASS_MASK;
211 writel(reg, &pll->pll_base);
212 debug("%s: base = 0x%08X\n", __func__, reg);
213
214
215 reg = readl(&pll->pll_misc);
216 if (pllinfo->lock_ena < 32)
217 reg |= (1 << pllinfo->lock_ena);
218 writel(reg, &pll->pll_misc);
219 debug("%s: misc = 0x%08X\n", __func__, reg);
220
221
222 reg = readl(&pll->pll_base);
223 reg |= PLL_ENABLE_MASK;
224 writel(reg, &pll->pll_base);
225 debug("%s: base final = 0x%08X\n", __func__, reg);
226
227 return 0;
228}
229
230void init_pllx(void)
231{
232 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
233 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
234 int soc_type, sku_info, chip_sku;
235 enum clock_osc_freq osc;
236 struct clk_pll_table *sel;
237 debug("%s entry\n", __func__);
238
239
240 soc_type = tegra_get_chip();
241 debug("%s: SoC = 0x%02X\n", __func__, soc_type);
242
243
244 sku_info = tegra_get_sku_info();
245 debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
246
247
248 chip_sku = tegra_get_chip_sku();
249 debug("%s: Chip SKU = %d\n", __func__, chip_sku);
250
251
252 osc = clock_get_osc_freq();
253 debug("%s: osc = %d\n", __func__, osc);
254
255
256 sel = &tegra_pll_x_table[chip_sku][osc];
257 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
258}
259
260void enable_cpu_clock(int enable)
261{
262 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
263 u32 clk;
264 debug("%s entry\n", __func__);
265
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272
273
274 if (enable) {
275
276 init_pllx();
277
278
279 udelay(PLL_STABILIZATION_DELAY);
280
281 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
282 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
283 }
284
285
286
287
288
289 clk = readl(&clkrst->crc_clk_cpu_cmplx);
290 clk |= 1 << CPU1_CLK_STP_SHIFT;
291 if (get_num_cpus() == 4)
292 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
293
294
295 clk &= ~CPU0_CLK_STP_MASK;
296 clk |= !enable << CPU0_CLK_STP_SHIFT;
297 writel(clk, &clkrst->crc_clk_cpu_cmplx);
298
299 clock_enable(PERIPH_ID_CPU);
300}
301
302static int is_cpu_powered(void)
303{
304 return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
305 pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
306}
307
308static void remove_cpu_io_clamps(void)
309{
310 u32 reg;
311 debug("%s entry\n", __func__);
312
313
314 reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
315 reg |= CPU_CLMP;
316 tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));
317
318
319 udelay(IO_STABILIZATION_DELAY);
320}
321
322void powerup_cpu(void)
323{
324 u32 reg;
325 int timeout = IO_STABILIZATION_DELAY;
326 debug("%s entry\n", __func__);
327
328 if (!is_cpu_powered()) {
329
330 reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
331 pmc_pwrgate_toggle));
332 reg &= PARTID_CP;
333 reg |= START_CP;
334 tegra_pmc_writel(reg,
335 offsetof(struct pmc_ctlr,
336 pmc_pwrgate_toggle));
337
338
339 while (!is_cpu_powered()) {
340 if (timeout-- == 0)
341 printf("CPU failed to power up!\n");
342 else
343 udelay(10);
344 }
345
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349
350
351
352 remove_cpu_io_clamps();
353 }
354}
355
356void reset_A9_cpu(int reset)
357{
358
359
360
361
362
363
364
365 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
366 int num_cpus = get_num_cpus();
367 int cpu;
368
369 debug("%s entry\n", __func__);
370
371 for (cpu = 1; cpu < num_cpus; cpu++)
372 reset_cmplx_set_enable(cpu, mask, 1);
373 reset_cmplx_set_enable(0, mask, reset);
374
375
376 reset_set_enable(PERIPH_ID_CPU, reset);
377}
378
379void clock_enable_coresight(int enable)
380{
381 u32 rst, src = 2;
382
383 debug("%s entry\n", __func__);
384 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
385 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
386
387 if (enable) {
388
389
390
391
392
393
394 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
395 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
396
397
398 rst = CORESIGHT_UNLOCK;
399 writel(rst, CSITE_CPU_DBG0_LAR);
400 writel(rst, CSITE_CPU_DBG1_LAR);
401 if (get_num_cpus() == 4) {
402 writel(rst, CSITE_CPU_DBG2_LAR);
403 writel(rst, CSITE_CPU_DBG3_LAR);
404 }
405 }
406}
407
408void halt_avp(void)
409{
410 debug("%s entry\n", __func__);
411
412 for (;;) {
413 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
414 FLOW_CTLR_HALT_COP_EVENTS);
415 }
416}
417