1menu "x86 architecture"
2 depends on X86
3
4config SYS_ARCH
5 default "x86"
6
7choice
8 prompt "Run U-Boot in 32/64-bit mode"
9 default X86_RUN_32BIT
10 help
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
14
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
18
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
21
22config X86_RUN_32BIT
23 bool "32-bit"
24 help
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
31
32config X86_RUN_64BIT
33 bool "64-bit"
34 select X86_64
35 select SPL
36 select SPL_SEPARATE_BSS
37 help
38 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
39 experimental and many features are missing. U-Boot SPL starts up,
40 runs through the 16-bit and 32-bit init, then switches to 64-bit
41 mode and jumps to U-Boot proper.
42
43endchoice
44
45config X86_64
46 bool
47
48config SPL_X86_64
49 bool
50 depends on SPL
51
52choice
53 prompt "Mainboard vendor"
54 default VENDOR_EMULATION
55
56config VENDOR_ADVANTECH
57 bool "advantech"
58
59config VENDOR_CONGATEC
60 bool "congatec"
61
62config VENDOR_COREBOOT
63 bool "coreboot"
64
65config VENDOR_DFI
66 bool "dfi"
67
68config VENDOR_EFI
69 bool "efi"
70
71config VENDOR_EMULATION
72 bool "emulation"
73
74config VENDOR_GOOGLE
75 bool "Google"
76
77config VENDOR_INTEL
78 bool "Intel"
79
80endchoice
81
82
83config INTEL_MID
84 bool "Intel MID platform support"
85 select REGMAP
86 select SYSCON
87 help
88 Select to build a U-Boot capable of supporting Intel MID
89 (Mobile Internet Device) platform systems which do not have
90 the PCI legacy interfaces.
91
92 If you are building for a PC class system say N here.
93
94 Intel MID platforms are based on an Intel processor and
95 chipset which consume less power than most of the x86
96 derivatives.
97
98
99source "board/advantech/Kconfig"
100source "board/congatec/Kconfig"
101source "board/coreboot/Kconfig"
102source "board/dfi/Kconfig"
103source "board/efi/Kconfig"
104source "board/emulation/Kconfig"
105source "board/google/Kconfig"
106source "board/intel/Kconfig"
107
108
109source "arch/x86/cpu/apollolake/Kconfig"
110source "arch/x86/cpu/baytrail/Kconfig"
111source "arch/x86/cpu/braswell/Kconfig"
112source "arch/x86/cpu/broadwell/Kconfig"
113source "arch/x86/cpu/coreboot/Kconfig"
114source "arch/x86/cpu/ivybridge/Kconfig"
115source "arch/x86/cpu/efi/Kconfig"
116source "arch/x86/cpu/qemu/Kconfig"
117source "arch/x86/cpu/quark/Kconfig"
118source "arch/x86/cpu/queensbay/Kconfig"
119source "arch/x86/cpu/slimbootloader/Kconfig"
120source "arch/x86/cpu/tangier/Kconfig"
121
122
123
124config AHCI
125 default y
126
127config SYS_MALLOC_F_LEN
128 default 0x800
129
130config RAMBASE
131 hex
132 default 0x100000
133
134config XIP_ROM_SIZE
135 hex
136 depends on X86_RESET_VECTOR
137 default ROM_SIZE
138
139config CPU_ADDR_BITS
140 int
141 default 36
142
143config HPET_ADDRESS
144 hex
145 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
146
147config SMM_TSEG
148 bool
149 default n
150
151config SMM_TSEG_SIZE
152 hex
153
154config X86_RESET_VECTOR
155 bool
156 default n
157 select BINMAN
158
159
160
161
162
163
164
165
166
167
168
169
170
171config X86_16BIT_INIT
172 bool
173 depends on X86_RESET_VECTOR
174 default y if X86_RESET_VECTOR && !SPL
175 help
176 This is enabled when 16-bit init is in U-Boot proper
177
178config SPL_X86_16BIT_INIT
179 bool
180 depends on X86_RESET_VECTOR
181 default y if X86_RESET_VECTOR && SPL && !TPL
182 help
183 This is enabled when 16-bit init is in SPL
184
185config TPL_X86_16BIT_INIT
186 bool
187 depends on X86_RESET_VECTOR
188 default y if X86_RESET_VECTOR && TPL
189 help
190 This is enabled when 16-bit init is in TPL
191
192config X86_32BIT_INIT
193 bool
194 depends on X86_RESET_VECTOR
195 default y if X86_RESET_VECTOR && !SPL
196 help
197 This is enabled when 32-bit init is in U-Boot proper
198
199config SPL_X86_32BIT_INIT
200 bool
201 depends on X86_RESET_VECTOR
202 default y if X86_RESET_VECTOR && SPL
203 help
204 This is enabled when 32-bit init is in SPL
205
206config USE_EARLY_BOARD_INIT
207 bool
208
209config RESET_SEG_START
210 hex
211 depends on X86_RESET_VECTOR
212 default 0xffff0000
213
214config RESET_VEC_LOC
215 hex
216 depends on X86_RESET_VECTOR
217 default 0xfffffff0
218
219config SYS_X86_START16
220 hex
221 depends on X86_RESET_VECTOR
222 default 0xfffff800
223
224config HAVE_X86_FIT
225 bool
226 help
227 Enable inclusion of an Intel Firmware Interface Table (FIT) into the
228 image. This table is supposed to point to microcode and the like. So
229 far it is just a fixed table with the minimum set of headers, so that
230 it is actually present.
231
232config X86_LOAD_FROM_32_BIT
233 bool "Boot from a 32-bit program"
234 help
235 Define this to boot U-Boot from a 32-bit program which sets
236 the GDT differently. This can be used to boot directly from
237 any stage of coreboot, for example, bypassing the normal
238 payload-loading feature.
239
240config BOARD_ROMSIZE_KB_512
241 bool
242config BOARD_ROMSIZE_KB_1024
243 bool
244config BOARD_ROMSIZE_KB_2048
245 bool
246config BOARD_ROMSIZE_KB_4096
247 bool
248config BOARD_ROMSIZE_KB_8192
249 bool
250config BOARD_ROMSIZE_KB_16384
251 bool
252
253choice
254 prompt "ROM chip size"
255 depends on X86_RESET_VECTOR
256 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
257 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
258 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
259 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
260 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
261 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
262 help
263 Select the size of the ROM chip you intend to flash U-Boot on.
264
265 The build system will take care of creating a u-boot.rom file
266 of the matching size.
267
268config UBOOT_ROMSIZE_KB_512
269 bool "512 KB"
270 help
271 Choose this option if you have a 512 KB ROM chip.
272
273config UBOOT_ROMSIZE_KB_1024
274 bool "1024 KB (1 MB)"
275 help
276 Choose this option if you have a 1024 KB (1 MB) ROM chip.
277
278config UBOOT_ROMSIZE_KB_2048
279 bool "2048 KB (2 MB)"
280 help
281 Choose this option if you have a 2048 KB (2 MB) ROM chip.
282
283config UBOOT_ROMSIZE_KB_4096
284 bool "4096 KB (4 MB)"
285 help
286 Choose this option if you have a 4096 KB (4 MB) ROM chip.
287
288config UBOOT_ROMSIZE_KB_8192
289 bool "8192 KB (8 MB)"
290 help
291 Choose this option if you have a 8192 KB (8 MB) ROM chip.
292
293config UBOOT_ROMSIZE_KB_16384
294 bool "16384 KB (16 MB)"
295 help
296 Choose this option if you have a 16384 KB (16 MB) ROM chip.
297
298endchoice
299
300
301config UBOOT_ROMSIZE_KB
302 int
303 default 512 if UBOOT_ROMSIZE_KB_512
304 default 1024 if UBOOT_ROMSIZE_KB_1024
305 default 2048 if UBOOT_ROMSIZE_KB_2048
306 default 4096 if UBOOT_ROMSIZE_KB_4096
307 default 8192 if UBOOT_ROMSIZE_KB_8192
308 default 16384 if UBOOT_ROMSIZE_KB_16384
309
310
311config ROM_SIZE
312 hex
313 default 0x80000 if UBOOT_ROMSIZE_KB_512
314 default 0x100000 if UBOOT_ROMSIZE_KB_1024
315 default 0x200000 if UBOOT_ROMSIZE_KB_2048
316 default 0x400000 if UBOOT_ROMSIZE_KB_4096
317 default 0x800000 if UBOOT_ROMSIZE_KB_8192
318 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
319 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
320
321config HAVE_INTEL_ME
322 bool "Platform requires Intel Management Engine"
323 help
324 Newer higher-end devices have an Intel Management Engine (ME)
325 which is a very large binary blob (typically 1.5MB) which is
326 required for the platform to work. This enforces a particular
327 SPI flash format. You will need to supply the me.bin file in
328 your board directory.
329
330config X86_RAMTEST
331 bool "Perform a simple RAM test after SDRAM initialisation"
332 help
333 If there is something wrong with SDRAM then the platform will
334 often crash within U-Boot or the kernel. This option enables a
335 very simple RAM test that quickly checks whether the SDRAM seems
336 to work correctly. It is not exhaustive but can save time by
337 detecting obvious failures.
338
339config FLASH_DESCRIPTOR_FILE
340 string "Flash descriptor binary filename"
341 depends on HAVE_INTEL_ME || FSP_VERSION2
342 default "descriptor.bin"
343 help
344 The filename of the file to use as flash descriptor in the
345 board directory.
346
347config INTEL_ME_FILE
348 string "Intel Management Engine binary filename"
349 depends on HAVE_INTEL_ME
350 default "me.bin"
351 help
352 The filename of the file to use as Intel Management Engine in the
353 board directory.
354
355config USE_HOB
356 bool "Use HOB (Hand-Off Block)"
357 help
358 Select this option to access HOB (Hand-Off Block) data structures
359 and parse HOBs. This HOB infra structure can be reused with
360 different solutions across different platforms.
361
362config HAVE_FSP
363 bool "Add an Firmware Support Package binary"
364 depends on !EFI
365 select USE_HOB
366 select HAS_ROM
367 select ROM_NEEDS_BLOBS
368 help
369 Select this option to add an Firmware Support Package binary to
370 the resulting U-Boot image. It is a binary blob which U-Boot uses
371 to set up SDRAM and other chipset specific initialization.
372
373 Note: Without this binary U-Boot will not be able to set up its
374 SDRAM so will not boot.
375
376config USE_CAR
377 bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
378 default y if !HAVE_FSP
379 help
380 Select this option if your board uses CAR init code, typically in a
381 car.S file, to get some initial memory for code execution. This is
382 common with Intel CPUs which don't use FSP.
383
384choice
385 prompt "FSP version"
386 depends on HAVE_FSP
387 default FSP_VERSION1
388 help
389 Selects the FSP version to use. Intel has published several versions
390 of the FSP External Architecture Specification and this allows
391 selection of the version number used by a particular SoC.
392
393config FSP_VERSION1
394 bool "FSP version 1.x"
395 help
396 This covers versions 1.0 and 1.1a. See here for details:
397 https://github.com/IntelFsp/fsp/wiki
398
399config FSP_VERSION2
400 bool "FSP version 2.x"
401 help
402 This covers versions 2.0 and 2.1. See here for details:
403 https://github.com/IntelFsp/fsp/wiki
404
405endchoice
406
407config FSP_FILE
408 string "Firmware Support Package binary filename"
409 depends on FSP_VERSION1
410 default "fsp.bin"
411 help
412 The filename of the file to use as Firmware Support Package binary
413 in the board directory.
414
415config FSP_ADDR
416 hex "Firmware Support Package binary location"
417 depends on FSP_VERSION1
418 default 0xfffc0000
419 help
420 FSP is not Position Independent Code (PIC) and the whole FSP has to
421 be rebased if it is placed at a location which is different from the
422 perferred base address specified during the FSP build. Use Intel's
423 Binary Configuration Tool (BCT) to do the rebase.
424
425 The default base address of 0xfffc0000 indicates that the binary must
426 be located at offset 0xc0000 from the beginning of a 1MB flash device.
427
428if FSP_VERSION2
429
430config FSP_FILE_T
431 string "Firmware Support Package binary filename (Temp RAM)"
432 default "fsp_t.bin"
433 help
434 The filename of the file to use for the temporary-RAM init phase from
435 the Firmware Support Package binary. Put this in the board directory.
436 It is used to set up an initial area of RAM which can be used for the
437 stack and other purposes, while bringing up the main system DRAM.
438
439config FSP_ADDR_T
440 hex "Firmware Support Package binary location (Temp RAM)"
441 default 0xffff8000
442 help
443 FSP is not Position-Independent Code (PIC) and FSP components have to
444 be rebased if placed at a location which is different from the
445 perferred base address specified during the FSP build. Use Intel's
446 Binary Configuration Tool (BCT) to do the rebase.
447
448config FSP_FILE_M
449 string "Firmware Support Package binary filename (Memory Init)"
450 default "fsp_m.bin"
451 help
452 The filename of the file to use for the RAM init phase from the
453 Firmware Support Package binary. Put this in the board directory.
454 It is used to set up the main system DRAM and runs in SPL, once
455 temporary RAM (CAR) is working.
456
457config FSP_FILE_S
458 string "Firmware Support Package binary filename (Silicon Init)"
459 default "fsp_s.bin"
460 help
461 The filename of the file to use for the Silicon init phase from the
462 Firmware Support Package binary. Put this in the board directory.
463 It is used to set up the silicon to work correctly and must be
464 executed after DRAM is running.
465
466config IFWI_INPUT_FILE
467 string "Filename containing FIT (Firmware Interface Table) with IFWI"
468 default "fitimage.bin"
469 help
470 The IFWI is obtained by running a tool on this file to extract the
471 IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
472 microcode and other internal items.
473
474endif
475
476config FSP_TEMP_RAM_ADDR
477 hex
478 depends on FSP_VERSION1
479 default 0x2000000
480 help
481 Stack top address which is used in fsp_init() after DRAM is ready and
482 CAR is disabled.
483
484config FSP_SYS_MALLOC_F_LEN
485 hex
486 depends on FSP_VERSION1
487 default 0x100000
488 help
489 Additional size of malloc() pool before relocation.
490
491config FSP_USE_UPD
492 bool
493 depends on FSP_VERSION1
494 default y
495 help
496 Most FSPs use UPD data region for some FSP customization. But there
497 are still some FSPs that might not even have UPD. For such FSPs,
498 override this to n in their platform Kconfig files.
499
500config FSP_BROKEN_HOB
501 bool
502 depends on FSP_VERSION1
503 help
504 Indicate some buggy FSPs that does not report memory used by FSP
505 itself as reserved in the resource descriptor HOB. Select this to
506 tell U-Boot to do some additional work to ensure U-Boot relocation
507 do not overwrite the important boot service data which is used by
508 FSP, otherwise the subsequent call to fsp_notify() will fail.
509
510config ENABLE_MRC_CACHE
511 bool "Enable MRC cache"
512 depends on !EFI && !SYS_COREBOOT
513 help
514 Enable this feature to cause MRC data to be cached in NV storage
515 to be used for speeding up boot time on future reboots and/or
516 power cycles.
517
518 For platforms that use Intel FSP for the memory initialization,
519 please check FSP output HOB via U-Boot command 'fsp hob' to see
520 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
521 If such GUID does not exist, MRC cache is not available on such
522 platform (eg: Intel Queensbay), which means selecting this option
523 here does not make any difference.
524
525config HAVE_MRC
526 bool "Add a System Agent binary"
527 select HAS_ROM
528 select ROM_NEEDS_BLOBS
529 depends on !HAVE_FSP
530 help
531 Select this option to add a System Agent binary to
532 the resulting U-Boot image. MRC stands for Memory Reference Code.
533 It is a binary blob which U-Boot uses to set up SDRAM.
534
535 Note: Without this binary U-Boot will not be able to set up its
536 SDRAM so will not boot.
537
538config CACHE_MRC_BIN
539 bool
540 depends on HAVE_MRC
541 default n
542 help
543 Enable caching for the memory reference code binary. This uses an
544 MTRR (memory type range register) to turn on caching for the section
545 of SPI flash that contains the memory reference code. This makes
546 SDRAM init run faster.
547
548config CACHE_MRC_SIZE_KB
549 int
550 depends on HAVE_MRC
551 default 512
552 help
553 Sets the size of the cached area for the memory reference code.
554 This ends at the end of SPI flash (address 0xffffffff) and is
555 measured in KB. Typically this is set to 512, providing for 0.5MB
556 of cached space.
557
558config DCACHE_RAM_BASE
559 hex
560 depends on HAVE_MRC
561 help
562 Sets the base of the data cache area in memory space. This is the
563 start address of the cache-as-RAM (CAR) area and the address varies
564 depending on the CPU. Once CAR is set up, read/write memory becomes
565 available at this address and can be used temporarily until SDRAM
566 is working.
567
568config DCACHE_RAM_SIZE
569 hex
570 depends on HAVE_MRC
571 default 0x40000
572 help
573 Sets the total size of the data cache area in memory space. This
574 sets the size of the cache-as-RAM (CAR) area. Note that much of the
575 CAR space is required by the MRC. The CAR space available to U-Boot
576 is normally at the start and typically extends to 1/4 or 1/2 of the
577 available size.
578
579config DCACHE_RAM_MRC_VAR_SIZE
580 hex
581 depends on HAVE_MRC
582 help
583 This is the amount of CAR (Cache as RAM) reserved for use by the
584 memory reference code. This depends on the implementation of the
585 memory reference code and must be set correctly or the board will
586 not boot.
587
588config HAVE_REFCODE
589 bool "Add a Reference Code binary"
590 help
591 Select this option to add a Reference Code binary to the resulting
592 U-Boot image. This is an Intel binary blob that handles system
593 initialisation, in this case the PCH and System Agent.
594
595 Note: Without this binary (on platforms that need it such as
596 broadwell) U-Boot will be missing some critical setup steps.
597 Various peripherals may fail to work.
598
599config HAVE_MICROCODE
600 bool "Board requires a microcode binary"
601 default y if !FSP_VERSION2
602 help
603 Enable this if the board requires microcode to be loaded on boot.
604 Typically this is handed by the FSP for modern boards, but for
605 some older boards, it must be programmed by U-Boot, and that form
606 part of the image.
607
608config SMP
609 bool "Enable Symmetric Multiprocessing"
610 default n
611 help
612 Enable use of more than one CPU in U-Boot and the Operating System
613 when loaded. Each CPU will be started up and information can be
614 obtained using the 'cpu' command. If this option is disabled, then
615 only one CPU will be enabled regardless of the number of CPUs
616 available.
617
618config SMP_AP_WORK
619 bool
620 depends on SMP
621 help
622 Allow APs to do other work after initialisation instead of going
623 to sleep.
624
625config MAX_CPUS
626 int "Maximum number of CPUs permitted"
627 depends on SMP
628 default 4
629 help
630 When using multi-CPU chips it is possible for U-Boot to start up
631 more than one CPU. The stack memory used by all of these CPUs is
632 pre-allocated so at present U-Boot wants to know the maximum
633 number of CPUs that may be present. Set this to at least as high
634 as the number of CPUs in your system (it uses about 4KB of RAM for
635 each CPU).
636
637config AP_STACK_SIZE
638 hex
639 depends on SMP
640 default 0x1000
641 help
642 Each additional CPU started by U-Boot requires its own stack. This
643 option sets the stack size used by each CPU and directly affects
644 the memory used by this initialisation process. Typically 4KB is
645 enough space.
646
647config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
648 bool
649 help
650 This option indicates that the turbo mode setting is not package
651 scoped. i.e. turbo_enable() needs to be called on not just the
652 bootstrap processor (BSP).
653
654config HAVE_VGA_BIOS
655 bool "Add a VGA BIOS image"
656 help
657 Select this option if you have a VGA BIOS image that you would
658 like to add to your ROM.
659
660config VGA_BIOS_FILE
661 string "VGA BIOS image filename"
662 depends on HAVE_VGA_BIOS
663 default "vga.bin"
664 help
665 The filename of the VGA BIOS image in the board directory.
666
667config VGA_BIOS_ADDR
668 hex "VGA BIOS image location"
669 depends on HAVE_VGA_BIOS
670 default 0xfff90000
671 help
672 The location of VGA BIOS image in the SPI flash. For example, base
673 address of 0xfff90000 indicates that the image will be put at offset
674 0x90000 from the beginning of a 1MB flash device.
675
676config HAVE_VBT
677 bool "Add a Video BIOS Table (VBT) image"
678 depends on HAVE_FSP
679 help
680 Select this option if you have a Video BIOS Table (VBT) image that
681 you would like to add to your ROM. This is normally required if you
682 are using an Intel FSP firmware that is complaint with spec 1.1 or
683 later to initialize the integrated graphics device (IGD).
684
685 Video BIOS Table, or VBT, provides platform and board specific
686 configuration information to the driver that is not discoverable
687 or available through other means. By other means the most used
688 method here is to read EDID table from the attached monitor, over
689 Display Data Channel (DDC) using two pin I2C serial interface. VBT
690 configuration is related to display hardware and is available via
691 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
692
693config VBT_FILE
694 string "Video BIOS Table (VBT) image filename"
695 depends on HAVE_VBT
696 default "vbt.bin"
697 help
698 The filename of the file to use as Video BIOS Table (VBT) image
699 in the board directory.
700
701config VBT_ADDR
702 hex "Video BIOS Table (VBT) image location"
703 depends on HAVE_VBT
704 default 0xfff90000
705 help
706 The location of Video BIOS Table (VBT) image in the SPI flash. For
707 example, base address of 0xfff90000 indicates that the image will
708 be put at offset 0x90000 from the beginning of a 1MB flash device.
709
710config VIDEO_FSP
711 bool "Enable FSP framebuffer driver support"
712 depends on HAVE_VBT && DM_VIDEO
713 help
714 Turn on this option to enable a framebuffer driver when U-Boot is
715 using Video BIOS Table (VBT) image for FSP firmware to initialize
716 the integrated graphics device.
717
718config ROM_TABLE_ADDR
719 hex
720 default 0xf0000
721 help
722 All x86 tables happen to like the address range from 0x0f0000
723 to 0x100000. We use 0xf0000 as the starting address to store
724 those tables, including PIRQ routing table, Multi-Processor
725 table and ACPI table.
726
727config ROM_TABLE_SIZE
728 hex
729 default 0x10000
730
731config HAVE_ITSS
732 bool "Enable ITSS"
733 help
734 Select this to include the driver for the Interrupt Timer
735 Subsystem (ITSS) which is found on several Intel devices.
736
737config HAVE_P2SB
738 bool "Enable P2SB"
739 depends on P2SB
740 help
741 Select this to include the driver for the Primary to
742 Sideband Bridge (P2SB) which is found on several Intel
743 devices.
744
745menu "System tables"
746 depends on !EFI && !SYS_COREBOOT
747
748config GENERATE_PIRQ_TABLE
749 bool "Generate a PIRQ table"
750 default n
751 help
752 Generate a PIRQ routing table for this board. The PIRQ routing table
753 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
754 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
755 It specifies the interrupt router information as well how all the PCI
756 devices' interrupt pins are wired to PIRQs.
757
758config GENERATE_SFI_TABLE
759 bool "Generate a SFI (Simple Firmware Interface) table"
760 help
761 The Simple Firmware Interface (SFI) provides a lightweight method
762 for platform firmware to pass information to the operating system
763 via static tables in memory. Kernel SFI support is required to
764 boot on SFI-only platforms. If you have ACPI tables then these are
765 used instead.
766
767 U-Boot writes this table in write_sfi_table() just before booting
768 the OS.
769
770 For more information, see http://simplefirmware.org
771
772config GENERATE_MP_TABLE
773 bool "Generate an MP (Multi-Processor) table"
774 default n
775 help
776 Generate an MP (Multi-Processor) table for this board. The MP table
777 provides a way for the operating system to support for symmetric
778 multiprocessing as well as symmetric I/O interrupt handling with
779 the local APIC and I/O APIC.
780
781config GENERATE_ACPI_TABLE
782 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
783 default n
784 select QFW if QEMU
785 help
786 The Advanced Configuration and Power Interface (ACPI) specification
787 provides an open standard for device configuration and management
788 by the operating system. It defines platform-independent interfaces
789 for configuration and power management monitoring.
790
791config ACPI_GNVS_EXTERNAL
792 bool
793 help
794 Put the GNVS (Global Non-Volatile Sleeping) table separate from the
795 DSDT and add a pointer to the table from the DSDT. This allows
796 U-Boot to better control the address of the GNVS.
797
798endmenu
799
800config HAVE_ACPI_RESUME
801 bool "Enable ACPI S3 resume"
802 select ENABLE_MRC_CACHE
803 help
804 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
805 state where all system context is lost except system memory. U-Boot
806 is responsible for restoring the machine state as it was before sleep.
807 It needs restore the memory controller, without overwriting memory
808 which is not marked as reserved. For the peripherals which lose their
809 registers, U-Boot needs to write the original value. When everything
810 is done, U-Boot needs to find out the wakeup vector provided by OSes
811 and jump there.
812
813config S3_VGA_ROM_RUN
814 bool "Re-run VGA option ROMs on S3 resume"
815 depends on HAVE_ACPI_RESUME
816 help
817 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
818 this is needed when graphics console is being used in the kernel.
819
820 Turning it off can reduce some resume time, but be aware that your
821 graphics console won't work without VGA options ROMs. Set it to N
822 if your kernel is only on a serial console.
823
824config STACK_SIZE_RESUME
825 hex
826 depends on HAVE_ACPI_RESUME
827 default 0x1000
828 help
829 Estimated U-Boot's runtime stack size that needs to be reserved
830 during an ACPI S3 resume.
831
832config MAX_PIRQ_LINKS
833 int
834 default 8
835 help
836 This variable specifies the number of PIRQ interrupt links which are
837 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
838 Some newer chipsets offer more than four links, commonly up to PIRQH.
839
840config IRQ_SLOT_COUNT
841 int
842 default 128
843 help
844 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
845 which in turns forms a table of exact 4KiB. The default value 128
846 should be enough for most boards. If this does not fit your board,
847 change it according to your needs.
848
849config PCIE_ECAM_BASE
850 hex
851 default 0xe0000000
852 help
853 This is the memory-mapped address of PCI configuration space, which
854 is only available through the Enhanced Configuration Access
855 Mechanism (ECAM) with PCI Express. It can be set up almost
856 anywhere. Before it is set up, it is possible to access PCI
857 configuration space through I/O access, but memory access is more
858 convenient. Using this, PCI can be scanned and configured. This
859 should be set to a region that does not conflict with memory
860 assigned to PCI devices - i.e. the memory and prefetch regions, as
861 passed to pci_set_region().
862
863config PCIE_ECAM_SIZE
864 hex
865 default 0x10000000
866 help
867 This is the size of memory-mapped address of PCI configuration space,
868 which is only available through the Enhanced Configuration Access
869 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
870 so a default 0x10000000 size covers all of the 256 buses which is the
871 maximum number of PCI buses as defined by the PCI specification.
872
873config I8259_PIC
874 bool "Enable Intel 8259 compatible interrupt controller"
875 default y
876 help
877 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
878 slave) interrupt controllers. Include this to have U-Boot set up
879 the interrupt correctly.
880
881config APIC
882 bool "Enable Intel Advanced Programmable Interrupt Controller"
883 default y
884 help
885 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
886 for catching interrupts and distributing them to one or more CPU
887 cores. In most cases there are some LAPICs (local) for each core and
888 one I/O APIC. This conjunction is found on most modern x86 systems.
889
890config PINCTRL_ICH6
891 bool
892 help
893 Intel ICH6 compatible chipset pinctrl driver. It needs to work
894 together with the ICH6 compatible gpio driver.
895
896config I8254_TIMER
897 bool
898 default y
899 help
900 Intel 8254 timer contains three counters which have fixed uses.
901 Include this to have U-Boot set up the timer correctly.
902
903config SEABIOS
904 bool "Support booting SeaBIOS"
905 help
906 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
907 It can run in an emulator or natively on X86 hardware with the use
908 of coreboot/U-Boot. By turning on this option, U-Boot prepares
909 all the configuration tables that are necessary to boot SeaBIOS.
910
911 Check http://www.seabios.org/SeaBIOS for details.
912
913config HIGH_TABLE_SIZE
914 hex "Size of configuration tables which reside in high memory"
915 default 0x10000
916 depends on SEABIOS
917 help
918 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
919 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
920 puts a copy of configuration tables in high memory region which
921 is reserved on the stack before relocation. The region size is
922 determined by this option.
923
924 Increse it if the default size does not fit the board's needs.
925 This is most likely due to a large ACPI DSDT table is used.
926
927config INTEL_CAR_CQOS
928 bool "Support Intel Cache Quality of Service"
929 help
930 Cache Quality of Service allows more fine-grained control of cache
931 usage. As result, it is possible to set up a portion of L2 cache for
932 CAR and use the remainder for actual caching.
933
934
935
936
937
938config CACHE_QOS_SIZE_PER_BIT
939 hex
940 depends on INTEL_CAR_CQOS
941 default 0x20000
942
943config X86_OFFSET_U_BOOT
944 hex "Offset of U-Boot in ROM image"
945 depends on HAVE_SYS_TEXT_BASE
946 default SYS_TEXT_BASE
947
948config X86_OFFSET_SPL
949 hex "Offset of SPL in ROM image"
950 depends on SPL && X86
951 default SPL_TEXT_BASE
952
953config ACPI_GPE
954 bool "Support ACPI general-purpose events"
955 help
956 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
957 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
958 needs access to these interrupts. This can happen when it uses a
959 peripheral that is set up to use GPEs and so cannot use the normal
960 GPIO mechanism for polling an input.
961
962 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
963
964config SPL_ACPI_GPE
965 bool "Support ACPI general-purpose events in SPL"
966 help
967 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
968 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
969 needs access to these interrupts. This can happen when it uses a
970 peripheral that is set up to use GPEs and so cannot use the normal
971 GPIO mechanism for polling an input.
972
973 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
974
975config TPL_ACPI_GPE
976 bool "Support ACPI general-purpose events in TPL"
977 help
978 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
979 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
980 needs access to these interrupts. This can happen when it uses a
981 peripheral that is set up to use GPEs and so cannot use the normal
982 GPIO mechanism for polling an input.
983
984 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
985
986config SA_PCIEX_LENGTH
987 hex
988 default 0x10000000 if (PCIEX_LENGTH_256MB)
989 default 0x8000000 if (PCIEX_LENGTH_128MB)
990 default 0x4000000 if (PCIEX_LENGTH_64MB)
991 default 0x10000000
992 help
993 This option allows you to select length of PCIEX region.
994
995config PCIEX_LENGTH_256MB
996 bool
997
998config PCIEX_LENGTH_128MB
999 bool
1000
1001config PCIEX_LENGTH_64MB
1002 bool
1003
1004config INTEL_SOC
1005 bool
1006 help
1007 This is enabled on Intel SoCs that can support various advanced
1008 features such as power management (requiring asm/arch/pm.h), system
1009 agent (asm/arch/systemagent.h) and an I/O map for ACPI
1010 (asm/arch/iomap.h).
1011
1012 This cannot be selected in a defconfig file. It must be enabled by a
1013 'select' in the SoC's Kconfig.
1014
1015if INTEL_SOC
1016
1017config INTEL_ACPIGEN
1018 bool "Support ACPI table generation for Intel SoCs"
1019 depends on ACPIGEN
1020 help
1021 This option adds some functions used for programmatic generation of
1022 ACPI tables on Intel SoCs. This provides features for writing CPU
1023 information such as P states and T stages. Also included is a way
1024 to create a GNVS table and set it up.
1025
1026config INTEL_GMA_ACPI
1027 bool "Generate ACPI table for Intel GMA graphics"
1028 help
1029 The Intel GMA graphics driver in Linux expects an ACPI table
1030 which describes the layout of the registers and the display
1031 connected to the device. Enable this option to create this
1032 table so that graphics works correctly.
1033
1034config INTEL_GENERIC_WIFI
1035 bool "Enable generation of ACPI tables for Intel WiFi"
1036 help
1037 Select this option to provide code to a build generic WiFi ACPI table
1038 for Intel WiFi devices. This is not a WiFi driver and offers no
1039 network functionality. It is only here to generate the ACPI tables
1040 required by Linux.
1041
1042config INTEL_GMA_SWSMISCI
1043 bool
1044 help
1045 Select this option for Atom-based platforms which use the SWSMISCI
1046 register (0xe0) rather than the SWSCI register (0xe8).
1047
1048endif
1049
1050endmenu
1051
