LXR uboot/arch/xtensa/lib/cache.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2008 - 2013 Tensilica Inc.
   4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
   5 */
   6
   7#include <common.h>
   8#include <cpu_func.h>
   9#include <asm/cache.h>
  10
  11/*
  12 * We currently run always with caches enabled when running from memory.
  13 * Xtensa version D or later will support changing cache behavior, so
  14 * we could implement it if necessary.
  15 */
  16
  17int dcache_status(void)
  18{
  19        return 1;
  20}
  21
  22void dcache_enable(void)
  23{
  24}
  25
  26void dcache_disable(void)
  27{
  28}
  29
  30void flush_cache(ulong start_addr, ulong size)
  31{
  32        __flush_invalidate_dcache_range(start_addr, size);
  33        __invalidate_icache_range(start_addr, size);
  34}
  35
  36void flush_dcache_all(void)
  37{
  38        __flush_dcache_all();
  39        __invalidate_icache_all();
  40}
  41
  42void flush_dcache_range(ulong start_addr, ulong end_addr)
  43{
  44        __flush_invalidate_dcache_range(start_addr, end_addr - start_addr);
  45}
  46
  47void invalidate_dcache_range(ulong start, ulong stop)
  48{
  49        __invalidate_dcache_range(start, stop - start);
  50}
  51
  52void invalidate_dcache_all(void)
  53{
  54        __invalidate_dcache_all();
  55}
  56
  57void invalidate_icache_all(void)
  58{
  59        __invalidate_icache_all();
  60}
  61