LXR uboot/board/bachmann/ot1200/ot1200

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2015, Bachmann electronic GmbH
   4 */
   5
   6#include <common.h>
   7#include <init.h>
   8#include <spl.h>
   9#include <asm/arch/mx6-ddr.h>
  10
  11/* Configure MX6Q/DUAL mmdc DDR io registers */
  12static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
  13        /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
  14        .dram_sdclk_0   = 0x00000028,
  15        .dram_sdclk_1   = 0x00000028,
  16        .dram_cas       = 0x00000028,
  17        .dram_ras       = 0x00000028,
  18        .dram_reset     = 0x00000028,
  19        /* SDCKE[0:1]: 100k pull-up */
  20        .dram_sdcke0    = 0x00003000,
  21        .dram_sdcke1    = 0x00003000,
  22        /* SDBA2: pull-up disabled */
  23        .dram_sdba2         = 0x00000000,
  24        /* SDODT[0:1]: 100k pull-up, 48 ohm */
  25        .dram_sdodt0    = 0x00000028,
  26        .dram_sdodt1    = 0x00000028,
  27        /* SDQS[0:7]: Differential input, 48 ohm */
  28        .dram_sdqs0     = 0x00000028,
  29        .dram_sdqs1     = 0x00000028,
  30        .dram_sdqs2     = 0x00000028,
  31        .dram_sdqs3     = 0x00000028,
  32        .dram_sdqs4     = 0x00000028,
  33        .dram_sdqs5     = 0x00000028,
  34        .dram_sdqs6     = 0x00000028,
  35        .dram_sdqs7     = 0x00000028,
  36        /* DQM[0:7]: Differential input, 48 ohm */
  37        .dram_dqm0      = 0x00000028,
  38        .dram_dqm1      = 0x00000028,
  39        .dram_dqm2      = 0x00000028,
  40        .dram_dqm3      = 0x00000028,
  41        .dram_dqm4      = 0x00000028,
  42        .dram_dqm5      = 0x00000028,
  43        .dram_dqm6      = 0x00000028,
  44        .dram_dqm7      = 0x00000028,
  45};
  46
  47/* Configure MX6Q/DUAL mmdc GRP io registers */
  48static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
  49        /* DDR3 */
  50        .grp_ddr_type    = 0x000c0000,
  51        .grp_ddrmode_ctl = 0x00020000,
  52        /* Disable DDR pullups */
  53        .grp_ddrpke      = 0x00000000,
  54        /* ADDR[00:16], SDBA[0:1]: 48 ohm */
  55        .grp_addds       = 0x00000028,
  56        /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
  57        .grp_ctlds       = 0x00000028,
  58        /* DATA[00:63]: Differential input, 48 ohm */
  59        .grp_ddrmode     = 0x00020000,
  60        .grp_b0ds        = 0x00000028,
  61        .grp_b1ds        = 0x00000028,
  62        .grp_b2ds        = 0x00000028,
  63        .grp_b3ds        = 0x00000028,
  64        .grp_b4ds        = 0x00000028,
  65        .grp_b5ds        = 0x00000028,
  66        .grp_b6ds        = 0x00000028,
  67        .grp_b7ds        = 0x00000028,
  68};
  69
  70static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
  71        /* Width of data bus: 0=16, 1=32, 2=64 */
  72        .dsize      = 2,
  73        /* config for full 4GB range so that get_mem_size() works */
  74        .cs_density = 32, /* 32Gb per CS */
  75        /* Single chip select */
  76        .ncs        = 1,
  77        .cs1_mirror = 0,        /* war 0 */
  78        .rtt_wr     = 1,        /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
  79        .rtt_nom    = 1,        /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
  80        .walat      = 1,        /* Write additional latency */
  81        .ralat      = 5,        /* Read additional latency */
  82        .mif3_mode  = 3,        /* Command prediction working mode */
  83        .bi_on      = 1,        /* Bank interleaving enabled */ /* war 1 */
  84        .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
  85        .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
  86        .refsel = 1,            /* Refresh cycles at 32KHz */
  87        .refr = 7,              /* 8 refresh commands per refresh cycle */
  88};
  89
  90/* MT41K128M16JT-125 */
  91static struct mx6_ddr3_cfg micron_2gib_1600 = {
  92        .mem_speed = 1600,
  93        .density   = 2,
  94        .width     = 16,
  95        .banks     = 8,
  96        .rowaddr   = 14,
  97        .coladdr   = 10,
  98        .pagesz    = 2,
  99        .trcd      = 1375,
 100        .trcmin    = 4875,
 101        .trasmin   = 3500,
 102        .SRT       = 1,
 103};
 104
 105static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
 106        /* write leveling calibration determine */
 107        .p0_mpwldectrl0 = 0x00260025,
 108        .p0_mpwldectrl1 = 0x00270021,
 109        .p1_mpwldectrl0 = 0x00180034,
 110        .p1_mpwldectrl1 = 0x00180024,
 111        /* Read DQS Gating calibration */
 112        .p0_mpdgctrl0   = 0x04380344,
 113        .p0_mpdgctrl1   = 0x0330032C,
 114        .p1_mpdgctrl0   = 0x0338033C,
 115        .p1_mpdgctrl1   = 0x032C0300,
 116        /* Read Calibration: DQS delay relative to DQ read access */
 117        .p0_mprddlctl   = 0x3C2E3238,
 118        .p1_mprddlctl   = 0x3A2E303C,
 119        /* Write Calibration: DQ/DM delay relative to DQS write access */
 120        .p0_mpwrdlctl   = 0x36384036,
 121        .p1_mpwrdlctl   = 0x442E4438,
 122};
 123
 124static void ot1200_spl_dram_init(void)
 125{
 126        mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
 127        mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
 128                     &micron_2gib_1600);
 129}
 130
 131/*
 132 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 133 * - we have a stack and a place to store GD, both in SRAM
 134 * - no variable global data is available
 135 */
 136void board_init_f(ulong dummy)
 137{
 138        /* setup AIPS and disable watchdog */
 139        arch_cpu_init();
 140
 141        /* iomux and setup of i2c */
 142        board_early_init_f();
 143
 144        /* setup GP timer */
 145        timer_init();
 146
 147        /* UART clocks enabled and gd valid - init serial console */
 148        preloader_console_init();
 149
 150        /* configure MMDC for SDRAM width/size and per-model calibration */
 151        ot1200_spl_dram_init();
 152}
 153