LXR uboot/board/freescale/t4rdb/eth.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2014 Freescale Semiconductor, Inc.
   4 *
   5 * Chunhe Lan <Chunhe.Lan@freescale.com>
   6 */
   7
   8#include <common.h>
   9#include <command.h>
  10#include <fdt_support.h>
  11#include <net.h>
  12#include <netdev.h>
  13#include <asm/mmu.h>
  14#include <asm/processor.h>
  15#include <asm/cache.h>
  16#include <asm/immap_85xx.h>
  17#include <asm/fsl_law.h>
  18#include <fsl_ddr_sdram.h>
  19#include <asm/fsl_serdes.h>
  20#include <asm/fsl_portals.h>
  21#include <asm/fsl_liodn.h>
  22#include <malloc.h>
  23#include <fm_eth.h>
  24#include <fsl_mdio.h>
  25#include <miiphy.h>
  26#include <phy.h>
  27#include <fsl_dtsec.h>
  28#include <asm/fsl_serdes.h>
  29#include <hwconfig.h>
  30
  31#include "../common/fman.h"
  32#include "t4rdb.h"
  33
  34void fdt_fixup_board_enet(void *fdt)
  35{
  36        return;
  37}
  38
  39int board_eth_init(struct bd_info *bis)
  40{
  41#if defined(CONFIG_FMAN_ENET)
  42        int i, interface;
  43        struct memac_mdio_info dtsec_mdio_info;
  44        struct memac_mdio_info tgec_mdio_info;
  45        struct mii_dev *dev;
  46        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  47        u32 srds_prtcl_s1, srds_prtcl_s2;
  48
  49        srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  50                                FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  51        srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  52        srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  53                                FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  54        srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  55
  56        dtsec_mdio_info.regs =
  57                (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
  58
  59        dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  60
  61        /* Register the 1G MDIO bus */
  62        fm_memac_mdio_init(bis, &dtsec_mdio_info);
  63
  64        tgec_mdio_info.regs =
  65                (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
  66        tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  67
  68        /* Register the 10G MDIO bus */
  69        fm_memac_mdio_init(bis, &tgec_mdio_info);
  70
  71        if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
  72                /* SGMII */
  73                fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
  74                fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
  75                fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
  76                fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
  77        } else {
  78                puts("Invalid SerDes1 protocol for T4240RDB\n");
  79        }
  80
  81        fm_disable_port(FM1_DTSEC5);
  82        fm_disable_port(FM1_DTSEC6);
  83
  84        for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  85                interface = fm_info_get_enet_if(i);
  86                switch (interface) {
  87                case PHY_INTERFACE_MODE_SGMII:
  88                        dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  89                        fm_info_set_mdio(i, dev);
  90                        break;
  91                default:
  92                        break;
  93                }
  94        }
  95
  96        for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  97                switch (fm_info_get_enet_if(i)) {
  98                case PHY_INTERFACE_MODE_XGMII:
  99                        dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 100                        fm_info_set_mdio(i, dev);
 101                        break;
 102                default:
 103                        break;
 104                }
 105        }
 106
 107#if (CONFIG_SYS_NUM_FMAN == 2)
 108        if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
 109                /* SGMII && XFI */
 110                fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
 111                fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
 112                fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
 113                fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
 114                fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 115                fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 116                fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
 117                fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
 118        } else {
 119                puts("Invalid SerDes2 protocol for T4240RDB\n");
 120        }
 121
 122        fm_disable_port(FM2_DTSEC5);
 123        fm_disable_port(FM2_DTSEC6);
 124        for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 125                interface = fm_info_get_enet_if(i);
 126                switch (interface) {
 127                case PHY_INTERFACE_MODE_SGMII:
 128                        dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 129                        fm_info_set_mdio(i, dev);
 130                        break;
 131                default:
 132                        break;
 133                }
 134        }
 135
 136        for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 137                switch (fm_info_get_enet_if(i)) {
 138                case PHY_INTERFACE_MODE_XGMII:
 139                        dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 140                        fm_info_set_mdio(i, dev);
 141                        break;
 142                default:
 143                        break;
 144                }
 145        }
 146#endif /* CONFIG_SYS_NUM_FMAN */
 147
 148        cpu_eth_init(bis);
 149#endif /* CONFIG_FMAN_ENET */
 150
 151        return pci_eth_init(bis);
 152}
 153