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10#include <common.h>
11#include <env.h>
12#include <fastboot.h>
13#include <fdt_support.h>
14#include <image.h>
15#include <init.h>
16#include <malloc.h>
17#include <net.h>
18#include <palmas.h>
19#include <sata.h>
20#include <serial.h>
21#include <usb.h>
22#include <errno.h>
23#include <asm/global_data.h>
24#include <asm/omap_common.h>
25#include <asm/omap_sec_common.h>
26#include <asm/emif.h>
27#include <asm/gpio.h>
28#include <asm/arch/gpio.h>
29#include <asm/arch/clock.h>
30#include <asm/arch/dra7xx_iodelay.h>
31#include <asm/arch/sys_proto.h>
32#include <asm/arch/mmc_host_def.h>
33#include <asm/arch/sata.h>
34#include <asm/arch/gpio.h>
35#include <asm/arch/omap.h>
36#include <usb.h>
37#include <linux/usb/gadget.h>
38#include <dwc3-uboot.h>
39#include <dwc3-omap-uboot.h>
40#include <ti-usb-phy-uboot.h>
41#include <mmc.h>
42#include <dm/uclass.h>
43#include <hang.h>
44
45#include "../common/board_detect.h"
46#include "mux_data.h"
47
48#ifdef CONFIG_SUPPORT_EMMC_BOOT
49static int board_bootmode_has_emmc(void);
50#endif
51
52#define board_is_x15() board_ti_is("BBRDX15_")
53#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
54 !strncmp("B.10", board_ti_get_rev(), 3))
55#define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
56 !strncmp("C.00", board_ti_get_rev(), 3))
57#define board_is_am572x_evm() board_ti_is("AM572PM_")
58#define board_is_am572x_evm_reva3() \
59 (board_ti_is("AM572PM_") && \
60 !strncmp("A.30", board_ti_get_rev(), 3))
61#define board_is_am574x_idk() board_ti_is("AM574IDK")
62#define board_is_am572x_idk() board_ti_is("AM572IDK")
63#define board_is_am571x_idk() board_ti_is("AM571IDK")
64#define board_is_bbai() board_ti_is("BBONE-AI")
65
66#define board_is_ti_idk() board_is_am574x_idk() || \
67 board_is_am572x_idk() || \
68 board_is_am571x_idk()
69
70#ifdef CONFIG_DRIVER_TI_CPSW
71#include <cpsw.h>
72#endif
73
74DECLARE_GLOBAL_DATA_PTR;
75
76#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
77#define GPIO_DDR_VTT_EN GPIO_TO_PIN(7, 11)
78
79
80#define OSD_TS_FT_BUS_ADDRESS 0
81#define OSD_TS_FT_CHIP_ADDRESS 0x38
82#define OSD_TS_FT_REG_ID 0xA3
83
84
85
86
87
88#define OSD_TS_FT_ID_5x46 0x54
89
90#define OSD_TS_FT_ID_5606 0x08
91
92#define SYSINFO_BOARD_NAME_MAX_LEN 45
93
94#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
95#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
96
97const struct omap_sysinfo sysinfo = {
98 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
99};
100
101static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
102 .dmm_lisa_map_3 = 0x80740300,
103 .is_ma_present = 0x1
104};
105
106static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
107 .dmm_lisa_map_3 = 0x80640100,
108 .is_ma_present = 0x1
109};
110
111static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
112 .dmm_lisa_map_2 = 0xc0600200,
113 .dmm_lisa_map_3 = 0x80600100,
114 .is_ma_present = 0x1
115};
116
117static const struct dmm_lisa_map_regs bbai_lisa_regs = {
118 .dmm_lisa_map_3 = 0x80640100,
119 .is_ma_present = 0x1
120};
121
122void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
123{
124 if (board_is_am571x_idk())
125 *dmm_lisa_regs = &am571x_idk_lisa_regs;
126 else if (board_is_am574x_idk())
127 *dmm_lisa_regs = &am574x_idk_lisa_regs;
128 else if (board_is_bbai())
129 *dmm_lisa_regs = &bbai_lisa_regs;
130 else
131 *dmm_lisa_regs = &beagle_x15_lisa_regs;
132}
133
134static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
135 .sdram_config_init = 0x61851b32,
136 .sdram_config = 0x61851b32,
137 .sdram_config2 = 0x08000000,
138 .ref_ctrl = 0x000040F1,
139 .ref_ctrl_final = 0x00001035,
140 .sdram_tim1 = 0xcccf36ab,
141 .sdram_tim2 = 0x308f7fda,
142 .sdram_tim3 = 0x409f88a8,
143 .read_idle_ctrl = 0x00050000,
144 .zq_config = 0x5007190b,
145 .temp_alert_config = 0x00000000,
146 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
147 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
148 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
149 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
150 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
151 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
152 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
153 .emif_rd_wr_lvl_rmp_win = 0x00000000,
154 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
155 .emif_rd_wr_lvl_ctl = 0x00000000,
156 .emif_rd_wr_exec_thresh = 0x00000305
157};
158
159
160static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
161 0x10040100,
162 0x00910091,
163 0x00950095,
164 0x009B009B,
165 0x009E009E,
166 0x00980098,
167 0x00340034,
168 0x00350035,
169 0x00340034,
170 0x00310031,
171 0x00340034,
172 0x007F007F,
173 0x007F007F,
174 0x007F007F,
175 0x007F007F,
176 0x007F007F,
177 0x00480048,
178 0x004A004A,
179 0x00520052,
180 0x00550055,
181 0x00500050,
182 0x00000000,
183 0x00600020,
184 0x40011080,
185 0x08102040,
186 0x0,
187 0x0,
188 0x0,
189 0x0,
190 0x0,
191 0x0,
192 0x0,
193 0x0,
194 0x0,
195 0x0
196};
197
198static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
199 .sdram_config_init = 0x61851b32,
200 .sdram_config = 0x61851b32,
201 .sdram_config2 = 0x08000000,
202 .ref_ctrl = 0x000040F1,
203 .ref_ctrl_final = 0x00001035,
204 .sdram_tim1 = 0xcccf36b3,
205 .sdram_tim2 = 0x308f7fda,
206 .sdram_tim3 = 0x407f88a8,
207 .read_idle_ctrl = 0x00050000,
208 .zq_config = 0x5007190b,
209 .temp_alert_config = 0x00000000,
210 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
211 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
212 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
213 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
214 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
215 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
216 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
217 .emif_rd_wr_lvl_rmp_win = 0x00000000,
218 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
219 .emif_rd_wr_lvl_ctl = 0x00000000,
220 .emif_rd_wr_exec_thresh = 0x00000305
221};
222
223static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
224 0x10040100,
225 0x00910091,
226 0x00950095,
227 0x009B009B,
228 0x009E009E,
229 0x00980098,
230 0x00340034,
231 0x00350035,
232 0x00340034,
233 0x00310031,
234 0x00340034,
235 0x007F007F,
236 0x007F007F,
237 0x007F007F,
238 0x007F007F,
239 0x007F007F,
240 0x00480048,
241 0x004A004A,
242 0x00520052,
243 0x00550055,
244 0x00500050,
245 0x00000000,
246 0x00600020,
247 0x40011080,
248 0x08102040,
249 0x0,
250 0x0,
251 0x0,
252 0x0,
253 0x0,
254 0x0,
255 0x0,
256 0x0,
257 0x0,
258 0x0
259};
260
261static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
262 .sdram_config_init = 0x61863332,
263 .sdram_config = 0x61863332,
264 .sdram_config2 = 0x08000000,
265 .ref_ctrl = 0x0000514d,
266 .ref_ctrl_final = 0x0000144a,
267 .sdram_tim1 = 0xd333887c,
268 .sdram_tim2 = 0x30b37fe3,
269 .sdram_tim3 = 0x409f8ad8,
270 .read_idle_ctrl = 0x00050000,
271 .zq_config = 0x5007190b,
272 .temp_alert_config = 0x00000000,
273 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
274 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
275 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
276 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
277 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
278 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
279 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
280 .emif_rd_wr_lvl_rmp_win = 0x00000000,
281 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
282 .emif_rd_wr_lvl_ctl = 0x00000000,
283 .emif_rd_wr_exec_thresh = 0x00000305
284};
285
286static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
287 .sdram_config_init = 0x61863332,
288 .sdram_config = 0x61863332,
289 .sdram_config2 = 0x08000000,
290 .ref_ctrl = 0x0000514d,
291 .ref_ctrl_final = 0x0000144a,
292 .sdram_tim1 = 0xd333887c,
293 .sdram_tim2 = 0x30b37fe3,
294 .sdram_tim3 = 0x409f8ad8,
295 .read_idle_ctrl = 0x00050000,
296 .zq_config = 0x5007190b,
297 .temp_alert_config = 0x00000000,
298 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
299 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
300 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
301 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
302 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
303 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
304 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
305 .emif_rd_wr_lvl_rmp_win = 0x00000000,
306 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
307 .emif_rd_wr_lvl_ctl = 0x00000000,
308 .emif_rd_wr_exec_thresh = 0x00000305,
309 .emif_ecc_ctrl_reg = 0xD0000001,
310 .emif_ecc_address_range_1 = 0x3FFF0000,
311 .emif_ecc_address_range_2 = 0x00000000
312};
313
314void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
315{
316 switch (emif_nr) {
317 case 1:
318 if (board_is_am571x_idk())
319 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
320 else if (board_is_am574x_idk())
321 *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
322 else
323 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
324 break;
325 case 2:
326 if (board_is_am574x_idk())
327 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
328 else
329 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
330 break;
331 }
332}
333
334void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
335{
336 switch (emif_nr) {
337 case 1:
338 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
339 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
340 break;
341 case 2:
342 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
343 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
344 break;
345 }
346}
347
348struct vcores_data beagle_x15_volts = {
349 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
350 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
351 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
352 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
353 .mpu.pmic = &tps659038,
354 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
355
356 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
357 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
358 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
359 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
360 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
361 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
362 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
363 .eve.addr = TPS659038_REG_ADDR_SMPS45,
364 .eve.pmic = &tps659038,
365 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
366
367 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
368 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
369 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
370 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
371 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
372 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
373 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
374 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
375 .gpu.pmic = &tps659038,
376 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
377
378 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
379 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
380 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
381 .core.addr = TPS659038_REG_ADDR_SMPS6,
382 .core.pmic = &tps659038,
383
384 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
385 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
386 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
387 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
388 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
389 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
390 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
391 .iva.addr = TPS659038_REG_ADDR_SMPS45,
392 .iva.pmic = &tps659038,
393 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
394};
395
396struct vcores_data am572x_idk_volts = {
397 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
398 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
399 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
400 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
401 .mpu.pmic = &tps659038,
402 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
403
404 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
405 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
406 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
407 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
408 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
409 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
410 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
411 .eve.addr = TPS659038_REG_ADDR_SMPS45,
412 .eve.pmic = &tps659038,
413 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
414
415 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
416 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
417 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
418 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
419 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
420 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
421 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
422 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
423 .gpu.pmic = &tps659038,
424 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
425
426 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
427 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
428 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
429 .core.addr = TPS659038_REG_ADDR_SMPS7,
430 .core.pmic = &tps659038,
431
432 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
433 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
434 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
435 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
436 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
437 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
438 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
439 .iva.addr = TPS659038_REG_ADDR_SMPS8,
440 .iva.pmic = &tps659038,
441 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
442};
443
444struct vcores_data am571x_idk_volts = {
445 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
446 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
447 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
448 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
449 .mpu.pmic = &tps659038,
450 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
451
452 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
453 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
454 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
455 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
456 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
457 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
458 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
459 .eve.addr = TPS659038_REG_ADDR_SMPS45,
460 .eve.pmic = &tps659038,
461 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
462
463 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
464 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
465 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
466 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
467 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
468 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
469 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
470 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
471 .gpu.pmic = &tps659038,
472 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
473
474 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
475 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
476 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
477 .core.addr = TPS659038_REG_ADDR_SMPS7,
478 .core.pmic = &tps659038,
479
480 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
481 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
482 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
483 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
484 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
485 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
486 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
487 .iva.addr = TPS659038_REG_ADDR_SMPS45,
488 .iva.pmic = &tps659038,
489 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
490};
491
492int get_voltrail_opp(int rail_offset)
493{
494 int opp;
495
496 switch (rail_offset) {
497 case VOLT_MPU:
498 opp = DRA7_MPU_OPP;
499 break;
500 case VOLT_CORE:
501 opp = DRA7_CORE_OPP;
502 break;
503 case VOLT_GPU:
504 opp = DRA7_GPU_OPP;
505 break;
506 case VOLT_EVE:
507 opp = DRA7_DSPEVE_OPP;
508 break;
509 case VOLT_IVA:
510 opp = DRA7_IVA_OPP;
511 break;
512 default:
513 opp = OPP_NOM;
514 }
515
516 return opp;
517}
518
519
520#ifdef CONFIG_SPL_BUILD
521
522static inline void setup_board_eeprom_env(void) { }
523
524
525void do_board_detect(void)
526{
527 int rc;
528
529 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
530 CONFIG_EEPROM_CHIP_ADDRESS);
531 if (rc)
532 printf("ti_i2c_eeprom_init failed %d\n", rc);
533
534#ifdef CONFIG_SUPPORT_EMMC_BOOT
535 rc = board_bootmode_has_emmc();
536 if (!rc)
537 rc = ti_emmc_boardid_get();
538 if (rc)
539 printf("ti_emmc_boardid_get failed %d\n", rc);
540#endif
541}
542
543#else
544
545
546void do_board_detect(void)
547{
548 char *bname = NULL;
549 int rc;
550
551 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
552 CONFIG_EEPROM_CHIP_ADDRESS);
553 if (rc)
554 printf("ti_i2c_eeprom_init failed %d\n", rc);
555
556#ifdef CONFIG_SUPPORT_EMMC_BOOT
557 rc = board_bootmode_has_emmc();
558 if (!rc)
559 rc = ti_emmc_boardid_get();
560 if (rc)
561 printf("ti_emmc_boardid_get failed %d\n", rc);
562#endif
563
564 if (board_is_x15())
565 bname = "BeagleBoard X15";
566 else if (board_is_am572x_evm())
567 bname = "AM572x EVM";
568 else if (board_is_am574x_idk())
569 bname = "AM574x IDK";
570 else if (board_is_am572x_idk())
571 bname = "AM572x IDK";
572 else if (board_is_am571x_idk())
573 bname = "AM571x IDK";
574 else if (board_is_bbai())
575 bname = "BeagleBone AI";
576
577 if (bname)
578 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
579 "Board: %s REV %s\n", bname, board_ti_get_rev());
580}
581
582static void setup_board_eeprom_env(void)
583{
584 char *name = "beagle_x15";
585 int rc;
586
587 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
588 CONFIG_EEPROM_CHIP_ADDRESS);
589 if (rc)
590 goto invalid_eeprom;
591
592 if (board_is_x15()) {
593 if (board_is_x15_revb1())
594 name = "beagle_x15_revb1";
595 else if (board_is_x15_revc())
596 name = "beagle_x15_revc";
597 else
598 name = "beagle_x15";
599 } else if (board_is_am572x_evm()) {
600 if (board_is_am572x_evm_reva3())
601 name = "am57xx_evm_reva3";
602 else
603 name = "am57xx_evm";
604 } else if (board_is_am574x_idk()) {
605 name = "am574x_idk";
606 } else if (board_is_am572x_idk()) {
607 name = "am572x_idk";
608 } else if (board_is_am571x_idk()) {
609 name = "am571x_idk";
610 } else if (board_is_bbai()) {
611 name = "am5729_beagleboneai";
612 } else {
613 printf("Unidentified board claims %s in eeprom header\n",
614 board_ti_get_name());
615 }
616
617invalid_eeprom:
618 set_board_info_env(name);
619}
620
621#endif
622
623void vcores_init(void)
624{
625 if (board_is_am572x_idk() || board_is_am574x_idk())
626 *omap_vcores = &am572x_idk_volts;
627 else if (board_is_am571x_idk())
628 *omap_vcores = &am571x_idk_volts;
629 else
630 *omap_vcores = &beagle_x15_volts;
631}
632
633void hw_data_init(void)
634{
635 *prcm = &dra7xx_prcm;
636 if (is_dra72x())
637 *dplls_data = &dra72x_dplls;
638 else if (is_dra76x())
639 *dplls_data = &dra76x_dplls;
640 else
641 *dplls_data = &dra7xx_dplls;
642 *ctrl = &dra7xx_ctrl;
643}
644
645bool am571x_idk_needs_lcd(void)
646{
647 bool needs_lcd;
648
649 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
650 if (gpio_get_value(GPIO_ETH_LCD))
651 needs_lcd = false;
652 else
653 needs_lcd = true;
654
655 gpio_free(GPIO_ETH_LCD);
656
657 return needs_lcd;
658}
659
660int board_init(void)
661{
662 gpmc_init();
663 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
664
665 return 0;
666}
667
668void am57x_idk_lcd_detect(void)
669{
670 int r = -ENODEV;
671 char *idk_lcd = "no";
672 struct udevice *dev;
673
674
675 if (!board_is_ti_idk())
676 return;
677
678
679 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
680 goto out;
681
682 r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
683 OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
684 if (r) {
685 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
686 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
687 r);
688
689 if (board_is_am571x_idk())
690 printf("%s: Touch screen detect failed: %d!\n",
691 __func__, r);
692 goto out;
693 }
694
695
696 r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
697 if (r < 0) {
698 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
699 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
700 OSD_TS_FT_REG_ID, r);
701 goto out;
702 }
703
704 switch (r) {
705 case OSD_TS_FT_ID_5606:
706 idk_lcd = "osd101t2045";
707 break;
708 case OSD_TS_FT_ID_5x46:
709 idk_lcd = "osd101t2587";
710 break;
711 default:
712 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
713 __func__, r);
714
715 }
716out:
717 env_set("idk_lcd", idk_lcd);
718
719
720
721
722
723 if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
724 !strncmp(idk_lcd, "no", 2)) {
725 printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
726 __func__);
727 hang();
728 }
729
730 return;
731}
732
733#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
734static int device_okay(const char *path)
735{
736 int node;
737
738 node = fdt_path_offset(gd->fdt_blob, path);
739 if (node < 0)
740 return 0;
741
742 return fdtdec_get_is_enabled(gd->fdt_blob, node);
743}
744#endif
745
746int board_late_init(void)
747{
748 setup_board_eeprom_env();
749 u8 val;
750 struct udevice *dev;
751
752
753
754
755
756 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
757
758
759
760
761
762 if (get_device_type() == HS_DEVICE)
763 env_set("boot_fit", "1");
764
765
766
767
768
769
770
771 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
772 &val);
773 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
774 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
775 val);
776
777 omap_die_id_serial();
778 omap_set_fastboot_vars();
779
780 am57x_idk_lcd_detect();
781
782
783 uclass_get_device(UCLASS_CLK, 0, &dev);
784
785 if (board_is_bbai())
786 env_set("console", "ttyS0,115200n8");
787
788#if !defined(CONFIG_SPL_BUILD)
789 board_ti_set_ethaddr(2);
790#endif
791
792#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
793 if (device_okay("/ocp/omap_dwc3_1@48880000"))
794 enable_usb_clocks(0);
795 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
796 enable_usb_clocks(1);
797#endif
798 return 0;
799}
800
801void set_muxconf_regs(void)
802{
803 do_set_mux32((*ctrl)->control_padconf_core_base,
804 early_padconf, ARRAY_SIZE(early_padconf));
805
806#ifdef CONFIG_SUPPORT_EMMC_BOOT
807 do_set_mux32((*ctrl)->control_padconf_core_base,
808 emmc_padconf, ARRAY_SIZE(emmc_padconf));
809#endif
810}
811
812#ifdef CONFIG_IODELAY_RECALIBRATION
813void recalibrate_iodelay(void)
814{
815 const struct pad_conf_entry *pconf;
816 const struct iodelay_cfg_entry *iod, *delta_iod;
817 int pconf_sz, iod_sz, delta_iod_sz = 0;
818 int ret;
819
820 if (board_is_am572x_idk()) {
821 pconf = core_padconf_array_essential_am572x_idk;
822 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
823 iod = iodelay_cfg_array_am572x_idk;
824 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
825 } else if (board_is_am574x_idk()) {
826 pconf = core_padconf_array_essential_am574x_idk;
827 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
828 iod = iodelay_cfg_array_am574x_idk;
829 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
830 } else if (board_is_am571x_idk()) {
831 pconf = core_padconf_array_essential_am571x_idk;
832 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
833 iod = iodelay_cfg_array_am571x_idk;
834 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
835 } else if (board_is_bbai()) {
836 pconf = core_padconf_array_essential_bbai;
837 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
838 iod = iodelay_cfg_array_bbai;
839 iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
840 } else {
841
842 pconf = core_padconf_array_essential_x15;
843 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
844
845 if (omap_revision() == DRA752_ES1_1) {
846 iod = iodelay_cfg_array_x15_sr1_1;
847 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
848 } else {
849
850 iod = iodelay_cfg_array_x15_sr2_0;
851 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
852 }
853 }
854
855
856 ret = __recalibrate_iodelay_start();
857 if (ret)
858 goto err;
859
860
861 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
862
863
864 if (board_is_x15() || board_is_am572x_evm()) {
865 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
866 board_is_x15_revc()) {
867 pconf = core_padconf_array_delta_x15_sr2_0;
868 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
869 } else {
870 pconf = core_padconf_array_delta_x15_sr1_1;
871 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
872 }
873 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
874 }
875
876 if (board_is_am571x_idk()) {
877 if (am571x_idk_needs_lcd()) {
878 pconf = core_padconf_array_vout_am571x_idk;
879 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
880 delta_iod = iodelay_cfg_array_am571x_idk_4port;
881 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
882
883 } else {
884 pconf = core_padconf_array_icss1eth_am571x_idk;
885 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
886 }
887 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
888 }
889
890
891 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
892 if (delta_iod_sz)
893 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
894 delta_iod_sz);
895
896err:
897
898 __recalibrate_iodelay_end(ret);
899}
900#endif
901
902#if defined(CONFIG_MMC)
903int board_mmc_init(struct bd_info *bis)
904{
905 omap_mmc_init(0, 0, 0, -1, -1);
906 omap_mmc_init(1, 0, 0, -1, -1);
907 return 0;
908}
909
910static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
911 .hw_rev = "rev11",
912 .unsupported_caps = MMC_CAP(MMC_HS_200) |
913 MMC_CAP(UHS_SDR104),
914 .max_freq = 96000000,
915};
916
917static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
918 .hw_rev = "rev11",
919 .unsupported_caps = MMC_CAP(MMC_HS_200) |
920 MMC_CAP(UHS_SDR104) |
921 MMC_CAP(UHS_SDR50),
922 .max_freq = 48000000,
923};
924
925const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
926{
927 switch (omap_revision()) {
928 case DRA752_ES1_0:
929 case DRA752_ES1_1:
930 if (addr == OMAP_HSMMC1_BASE)
931 return &am57x_es1_1_mmc1_fixups;
932 else
933 return &am57x_es1_1_mmc23_fixups;
934 default:
935 return NULL;
936 }
937}
938#endif
939
940#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
941int spl_start_uboot(void)
942{
943
944 if (serial_tstc() && serial_getc() == 'c')
945 return 1;
946
947#ifdef CONFIG_SPL_ENV_SUPPORT
948 env_init();
949 env_load();
950 if (env_get_yesno("boot_os") != 1)
951 return 1;
952#endif
953
954 return 0;
955}
956#endif
957
958#ifdef CONFIG_DRIVER_TI_CPSW
959
960
961#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
962#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
963#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
964#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
965#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
966#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
967#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
968#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
969#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
970#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
971
972static void cpsw_control(int enabled)
973{
974
975}
976
977static struct cpsw_slave_data cpsw_slaves[] = {
978 {
979 .slave_reg_ofs = 0x208,
980 .sliver_reg_ofs = 0xd80,
981 .phy_addr = 1,
982 },
983 {
984 .slave_reg_ofs = 0x308,
985 .sliver_reg_ofs = 0xdc0,
986 .phy_addr = 2,
987 },
988};
989
990static struct cpsw_platform_data cpsw_data = {
991 .mdio_base = CPSW_MDIO_BASE,
992 .cpsw_base = CPSW_BASE,
993 .mdio_div = 0xff,
994 .channels = 8,
995 .cpdma_reg_ofs = 0x800,
996 .slaves = 1,
997 .slave_data = cpsw_slaves,
998 .ale_reg_ofs = 0xd00,
999 .ale_entries = 1024,
1000 .host_port_reg_ofs = 0x108,
1001 .hw_stats_reg_ofs = 0x900,
1002 .bd_ram_ofs = 0x2000,
1003 .mac_control = (1 << 5),
1004 .control = cpsw_control,
1005 .host_port_num = 0,
1006 .version = CPSW_CTRL_VERSION_2,
1007};
1008
1009static u64 mac_to_u64(u8 mac[6])
1010{
1011 int i;
1012 u64 addr = 0;
1013
1014 for (i = 0; i < 6; i++) {
1015 addr <<= 8;
1016 addr |= mac[i];
1017 }
1018
1019 return addr;
1020}
1021
1022static void u64_to_mac(u64 addr, u8 mac[6])
1023{
1024 mac[5] = addr;
1025 mac[4] = addr >> 8;
1026 mac[3] = addr >> 16;
1027 mac[2] = addr >> 24;
1028 mac[1] = addr >> 32;
1029 mac[0] = addr >> 40;
1030}
1031
1032int board_eth_init(struct bd_info *bis)
1033{
1034 int ret;
1035 uint8_t mac_addr[6];
1036 uint32_t mac_hi, mac_lo;
1037 uint32_t ctrl_val;
1038 int i;
1039 u64 mac1, mac2;
1040 u8 mac_addr1[6], mac_addr2[6];
1041 int num_macs;
1042
1043
1044 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1045 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1046 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1047 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1048 mac_addr[2] = mac_hi & 0xFF;
1049 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1050 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1051 mac_addr[5] = mac_lo & 0xFF;
1052
1053 if (!env_get("ethaddr")) {
1054 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1055
1056 if (is_valid_ethaddr(mac_addr))
1057 eth_env_set_enetaddr("ethaddr", mac_addr);
1058 }
1059
1060 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1061 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1062 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1063 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1064 mac_addr[2] = mac_hi & 0xFF;
1065 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1066 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1067 mac_addr[5] = mac_lo & 0xFF;
1068
1069 if (!env_get("eth1addr")) {
1070 if (is_valid_ethaddr(mac_addr))
1071 eth_env_set_enetaddr("eth1addr", mac_addr);
1072 }
1073
1074 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1075 ctrl_val |= 0x22;
1076 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1077
1078
1079 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1080 board_is_am574x_idk()) {
1081 cpsw_data.slave_data[0].phy_addr = 0;
1082 cpsw_data.slave_data[1].phy_addr = 1;
1083 }
1084
1085 ret = cpsw_register(&cpsw_data);
1086 if (ret < 0)
1087 printf("Error %d registering CPSW switch\n", ret);
1088
1089
1090
1091
1092
1093 board_ti_get_eth_mac_addr(0, mac_addr1);
1094 board_ti_get_eth_mac_addr(1, mac_addr2);
1095
1096 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1097 mac1 = mac_to_u64(mac_addr1);
1098 mac2 = mac_to_u64(mac_addr2);
1099
1100
1101 num_macs = mac2 - mac1 + 1;
1102
1103 if (num_macs > 0 && num_macs <= 50) {
1104 for (i = 0; i < num_macs; i++) {
1105 u64_to_mac(mac1 + i, mac_addr);
1106 if (is_valid_ethaddr(mac_addr)) {
1107 eth_env_set_enetaddr_by_index("eth",
1108 i + 2,
1109 mac_addr);
1110 }
1111 }
1112 }
1113 }
1114
1115 return ret;
1116}
1117#endif
1118
1119#ifdef CONFIG_BOARD_EARLY_INIT_F
1120
1121static inline void vtt_regulator_enable(void)
1122{
1123 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1124 return;
1125
1126 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1127 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1128}
1129
1130int board_early_init_f(void)
1131{
1132 vtt_regulator_enable();
1133 return 0;
1134}
1135#endif
1136
1137#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1138int ft_board_setup(void *blob, struct bd_info *bd)
1139{
1140 ft_cpu_setup(blob, bd);
1141
1142 return 0;
1143}
1144#endif
1145
1146#ifdef CONFIG_SPL_LOAD_FIT
1147int board_fit_config_name_match(const char *name)
1148{
1149 if (board_is_x15()) {
1150 if (board_is_x15_revb1()) {
1151 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1152 return 0;
1153 } else if (board_is_x15_revc()) {
1154 if (!strcmp(name, "am57xx-beagle-x15-revc"))
1155 return 0;
1156 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1157 return 0;
1158 }
1159 } else if (board_is_am572x_evm() &&
1160 !strcmp(name, "am57xx-beagle-x15")) {
1161 return 0;
1162 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1163 return 0;
1164 } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1165 return 0;
1166 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1167 return 0;
1168 } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
1169 return 0;
1170 }
1171
1172 return -1;
1173}
1174#endif
1175
1176#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1177int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
1178{
1179 if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
1180 return -ENOTSUPP;
1181
1182 printf("Setting reboot to fastboot flag ...\n");
1183 env_set("dofastboot", "1");
1184 env_save();
1185 return 0;
1186}
1187#endif
1188
1189#ifdef CONFIG_SUPPORT_EMMC_BOOT
1190static int board_bootmode_has_emmc(void)
1191{
1192
1193 if (gd->arch.omap_boot_mode != 2)
1194 return -EIO;
1195
1196 return 0;
1197}
1198#endif
1199
1200#ifdef CONFIG_TI_SECURE_DEVICE
1201void board_fit_image_post_process(void **p_image, size_t *p_size)
1202{
1203 secure_boot_verify_image(p_image, p_size);
1204}
1205
1206void board_tee_image_process(ulong tee_image, size_t tee_size)
1207{
1208 secure_tee_install((u32)tee_image);
1209}
1210
1211U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1212#endif
1213
