1
2
3
4
5
6
7
8#include <common.h>
9#include <cpu_func.h>
10#include <log.h>
11#include <pci.h>
12#include <command.h>
13#include <asm/byteorder.h>
14#include <malloc.h>
15#include <asm/io.h>
16#include <fis.h>
17#include <sata.h>
18#include <libata.h>
19#include <sata.h>
20#include <linux/delay.h>
21
22#if CONFIG_IS_ENABLED(BLK)
23#include <dm.h>
24#include <blk.h>
25#include <dm/device-internal.h>
26#endif
27
28#include "sata_sil.h"
29
30#ifdef CONFIG_DM_PCI
31#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
32#else
33#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
34#endif
35
36
37struct sil_ops {
38 int *rev0;
39 int *rev1;
40 int (*scan)(struct udevice *dev);
41};
42
43static struct sata_info sata_info;
44
45static struct pci_device_id supported[] = {
46 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
47 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
48 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
49 {}
50};
51
52static void sil_sata_dump_fis(struct sata_fis_d2h *s)
53{
54 printf("Status FIS dump:\n");
55 printf("fis_type: %02x\n", s->fis_type);
56 printf("pm_port_i: %02x\n", s->pm_port_i);
57 printf("status: %02x\n", s->status);
58 printf("error: %02x\n", s->error);
59 printf("lba_low: %02x\n", s->lba_low);
60 printf("lba_mid: %02x\n", s->lba_mid);
61 printf("lba_high: %02x\n", s->lba_high);
62 printf("device: %02x\n", s->device);
63 printf("lba_low_exp: %02x\n", s->lba_low_exp);
64 printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
65 printf("lba_high_exp: %02x\n", s->lba_high_exp);
66 printf("res1: %02x\n", s->res1);
67 printf("sector_count: %02x\n", s->sector_count);
68 printf("sector_count_exp: %02x\n", s->sector_count_exp);
69}
70
71static const char *sata_spd_string(unsigned int speed)
72{
73 static const char * const spd_str[] = {
74 "1.5 Gbps",
75 "3.0 Gbps",
76 "6.0 Gbps",
77 };
78
79 if ((speed - 1) > 2)
80 return "<unknown>";
81
82 return spd_str[speed - 1];
83}
84
85static u32 ata_wait_register(void *reg, u32 mask,
86 u32 val, int timeout_msec)
87{
88 u32 tmp;
89
90 tmp = readl(reg);
91 while ((tmp & mask) == val && timeout_msec > 0) {
92 mdelay(1);
93 timeout_msec--;
94 tmp = readl(reg);
95 }
96
97 return tmp;
98}
99
100static void sil_config_port(void *port)
101{
102
103 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
104
105
106 writew(0x8000, port + PORT_DECODE_ERR_THRESH);
107 writew(0x8000, port + PORT_CRC_ERR_THRESH);
108 writew(0x8000, port + PORT_HSHK_ERR_THRESH);
109 writew(0x0000, port + PORT_DECODE_ERR_CNT);
110 writew(0x0000, port + PORT_CRC_ERR_CNT);
111 writew(0x0000, port + PORT_HSHK_ERR_CNT);
112
113
114 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
115
116
117 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
118}
119
120static int sil_init_port(void *port)
121{
122 u32 tmp;
123
124 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
125 ata_wait_register(port + PORT_CTRL_STAT,
126 PORT_CS_INIT, PORT_CS_INIT, 100);
127 tmp = ata_wait_register(port + PORT_CTRL_STAT,
128 PORT_CS_RDY, 0, 100);
129
130 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
131 return 1;
132
133 return 0;
134}
135
136static void sil_read_fis(struct sil_sata *sata, int tag,
137 struct sata_fis_d2h *fis)
138{
139 void *port = sata->port;
140 struct sil_prb *prb;
141 int i;
142 u32 *src, *dst;
143
144 prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
145 src = (u32 *)&prb->fis;
146 dst = (u32 *)fis;
147 for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
148 *dst++ = readl(src++);
149}
150
151static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
152 int tag)
153{
154 void *port = sata->port;
155 u64 paddr = virt_to_bus(sata->devno, pcmd);
156 u32 irq_mask, irq_stat;
157 int rc;
158
159 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
160
161
162 writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
163 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
164
165 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
166 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
167 0, 10000);
168
169
170 writel(irq_mask, port + PORT_IRQ_STAT);
171 irq_stat >>= PORT_IRQ_RAW_SHIFT;
172
173 if (irq_stat & PORT_IRQ_COMPLETE)
174 rc = 0;
175 else {
176
177 sil_init_port(port);
178 if (irq_stat & PORT_IRQ_ERROR)
179 rc = 1;
180 else
181 rc = 2;
182 }
183
184 return rc;
185}
186
187static int sil_cmd_set_feature(struct sil_sata *sata)
188{
189 struct sil_cmd_block cmdb, *pcmd = &cmdb;
190 struct sata_fis_d2h fis;
191 u8 udma_cap;
192 int ret;
193
194 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
195 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
196 pcmd->prb.fis.pm_port_c = (1 << 7);
197 pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
198 pcmd->prb.fis.features = SETFEATURES_XFER;
199
200
201 udma_cap = (u8)(sata->udma & 0xff);
202 debug("udma_cap %02x\n", udma_cap);
203
204 if (udma_cap == ATA_UDMA6)
205 pcmd->prb.fis.sector_count = XFER_UDMA_6;
206 if (udma_cap == ATA_UDMA5)
207 pcmd->prb.fis.sector_count = XFER_UDMA_5;
208 if (udma_cap == ATA_UDMA4)
209 pcmd->prb.fis.sector_count = XFER_UDMA_4;
210 if (udma_cap == ATA_UDMA3)
211 pcmd->prb.fis.sector_count = XFER_UDMA_3;
212
213 ret = sil_exec_cmd(sata, pcmd, 0);
214 if (ret) {
215 sil_read_fis(sata, 0, &fis);
216 printf("Err: exe cmd(0x%x).\n",
217 readl(sata->port + PORT_SERROR));
218 sil_sata_dump_fis(&fis);
219 return 1;
220 }
221
222 return 0;
223}
224
225static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
226{
227 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
228 sata->wcache = 1;
229 if (ata_id_has_flush(id))
230 sata->flush = 1;
231 if (ata_id_has_flush_ext(id))
232 sata->flush_ext = 1;
233}
234
235static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
236{
237#ifdef CONFIG_LBA48
238
239 if (ata_id_has_lba48(id)) {
240 sata->lba48 = 1;
241 debug("Device supports LBA48\n");
242 } else {
243 debug("Device supports LBA28\n");
244 }
245#endif
246
247 sil_sata_init_wcache(sata, id);
248 sil_cmd_set_feature(sata);
249}
250
251static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
252{
253 struct sil_cmd_block cmdb, *pcmd = &cmdb;
254 struct sata_fis_d2h fis;
255 int ret;
256
257 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
258 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
259 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
260 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
261 pcmd->prb.fis.pm_port_c = (1 << 7);
262 pcmd->prb.fis.command = ATA_CMD_ID_ATA;
263 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
264 pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
265 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
266
267 ret = sil_exec_cmd(sata, pcmd, 0);
268 if (ret) {
269 sil_read_fis(sata, 0, &fis);
270 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
271 sil_sata_dump_fis(&fis);
272 return 1;
273 }
274 ata_swap_buf_le16(id, ATA_ID_WORDS);
275
276 return 0;
277}
278
279static int sil_cmd_soft_reset(struct sil_sata *sata)
280{
281 struct sil_cmd_block cmdb, *pcmd = &cmdb;
282 struct sata_fis_d2h fis;
283 void *port = sata->port;
284 int ret;
285
286
287 if (sil_init_port(port)) {
288 printf("SRST: port %d not ready\n", sata->id);
289 return 1;
290 }
291
292 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
293
294 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
295 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
296 pcmd->prb.fis.pm_port_c = 0xf;
297
298 ret = sil_exec_cmd(sata, &cmdb, 0);
299 if (ret) {
300 sil_read_fis(sata, 0, &fis);
301 printf("SRST cmd error.\n");
302 sil_sata_dump_fis(&fis);
303 return 1;
304 }
305
306 return 0;
307}
308
309static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
310 u8 *buffer, int is_write)
311{
312 struct sil_cmd_block cmdb, *pcmd = &cmdb;
313 struct sata_fis_d2h fis;
314 u64 block;
315 int ret;
316
317 block = (u64)start;
318 memset(pcmd, 0, sizeof(struct sil_cmd_block));
319 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
320 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
321 pcmd->prb.fis.pm_port_c = (1 << 7);
322 if (is_write) {
323 pcmd->prb.fis.command = ATA_CMD_WRITE;
324 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
325 } else {
326 pcmd->prb.fis.command = ATA_CMD_READ;
327 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
328 }
329
330 pcmd->prb.fis.device = ATA_LBA;
331 pcmd->prb.fis.device |= (block >> 24) & 0xf;
332 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
333 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
334 pcmd->prb.fis.lba_low = block & 0xff;
335 pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
336
337 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
338 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
339 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
340
341 ret = sil_exec_cmd(sata, pcmd, 0);
342 if (ret) {
343 sil_read_fis(sata, 0, &fis);
344 printf("Err: rw cmd(0x%08x).\n",
345 readl(sata->port + PORT_SERROR));
346 sil_sata_dump_fis(&fis);
347 return 1;
348 }
349
350 return blkcnt;
351}
352
353static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
354 ulong blkcnt, u8 *buffer, int is_write)
355{
356 struct sil_cmd_block cmdb, *pcmd = &cmdb;
357 struct sata_fis_d2h fis;
358 u64 block;
359 int ret;
360
361 block = (u64)start;
362 memset(pcmd, 0, sizeof(struct sil_cmd_block));
363 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
364 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
365 pcmd->prb.fis.pm_port_c = (1 << 7);
366 if (is_write) {
367 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
368 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
369 } else {
370 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
371 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
372 }
373
374 pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
375 pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
376 pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
377 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
378 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
379 pcmd->prb.fis.lba_low = block & 0xff;
380 pcmd->prb.fis.device = ATA_LBA;
381 pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
382 pcmd->prb.fis.sector_count = blkcnt & 0xff;
383
384 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
385 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
386 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
387
388 ret = sil_exec_cmd(sata, pcmd, 0);
389 if (ret) {
390 sil_read_fis(sata, 0, &fis);
391 printf("Err: rw ext cmd(0x%08x).\n",
392 readl(sata->port + PORT_SERROR));
393 sil_sata_dump_fis(&fis);
394 return 1;
395 }
396
397 return blkcnt;
398}
399
400static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
401 lbaint_t blkcnt, const void *buffer,
402 int is_write)
403{
404 ulong start, blks, max_blks;
405 u8 *addr;
406
407 start = blknr;
408 blks = blkcnt;
409 addr = (u8 *)buffer;
410
411 max_blks = ATA_MAX_SECTORS;
412 do {
413 if (blks > max_blks) {
414 sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
415 start += max_blks;
416 blks -= max_blks;
417 addr += ATA_SECT_SIZE * max_blks;
418 } else {
419 sil_sata_rw_cmd(sata, start, blks, addr, is_write);
420 start += blks;
421 blks = 0;
422 addr += ATA_SECT_SIZE * blks;
423 }
424 } while (blks != 0);
425
426 return blkcnt;
427}
428
429static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
430 lbaint_t blkcnt, const void *buffer,
431 int is_write)
432{
433 ulong start, blks, max_blks;
434 u8 *addr;
435
436 start = blknr;
437 blks = blkcnt;
438 addr = (u8 *)buffer;
439
440 max_blks = ATA_MAX_SECTORS_LBA48;
441 do {
442 if (blks > max_blks) {
443 sil_sata_rw_cmd_ext(sata, start, max_blks,
444 addr, is_write);
445 start += max_blks;
446 blks -= max_blks;
447 addr += ATA_SECT_SIZE * max_blks;
448 } else {
449 sil_sata_rw_cmd_ext(sata, start, blks,
450 addr, is_write);
451 start += blks;
452 blks = 0;
453 addr += ATA_SECT_SIZE * blks;
454 }
455 } while (blks != 0);
456
457 return blkcnt;
458}
459
460static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
461{
462 struct sil_cmd_block cmdb, *pcmd = &cmdb;
463
464 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
465 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
466 pcmd->prb.fis.pm_port_c = (1 << 7);
467 pcmd->prb.fis.command = ATA_CMD_FLUSH;
468
469 sil_exec_cmd(sata, pcmd, 0);
470}
471
472static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
473{
474 struct sil_cmd_block cmdb, *pcmd = &cmdb;
475
476 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
477 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
478 pcmd->prb.fis.pm_port_c = (1 << 7);
479 pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
480
481 sil_exec_cmd(sata, pcmd, 0);
482}
483
484
485
486
487#if !CONFIG_IS_ENABLED(BLK)
488ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
489{
490 struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
491#else
492static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
493 void *buffer)
494{
495 struct sil_sata_priv *priv = dev_get_plat(dev);
496 int port_number = priv->port_num;
497 struct sil_sata *sata = priv->sil_sata_desc[port_number];
498#endif
499 ulong rc;
500
501 if (sata->lba48)
502 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
503 else
504 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
505
506 return rc;
507}
508
509
510
511
512#if !CONFIG_IS_ENABLED(BLK)
513ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
514{
515 struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
516#else
517ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
518 const void *buffer)
519{
520 struct sil_sata_priv *priv = dev_get_plat(dev);
521 int port_number = priv->port_num;
522 struct sil_sata *sata = priv->sil_sata_desc[port_number];
523#endif
524 ulong rc;
525
526 if (sata->lba48) {
527 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
528 if (sata->wcache && sata->flush_ext)
529 sil_sata_cmd_flush_cache_ext(sata);
530 } else {
531 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
532 if (sata->wcache && sata->flush)
533 sil_sata_cmd_flush_cache(sata);
534 }
535
536 return rc;
537}
538
539#if !CONFIG_IS_ENABLED(BLK)
540static int sil_init_sata(int dev)
541{
542#else
543static int sil_init_sata(struct udevice *uc_dev, int dev)
544{
545 struct sil_sata_priv *priv = dev_get_plat(uc_dev);
546#endif
547 struct sil_sata *sata;
548 void *port;
549 u32 tmp;
550 int cnt;
551
552 printf("SATA#%d:\n", dev);
553
554 port = (void *)sata_info.iobase[1] +
555 PORT_REGS_SIZE * (dev - sata_info.portbase);
556
557
558 writel(0x20c, port + PORT_PHY_CFG);
559
560
561 tmp = readl(port + PORT_CTRL_STAT);
562 if (tmp & PORT_CS_PORT_RST) {
563 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
564 tmp = ata_wait_register(port + PORT_CTRL_STAT,
565 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
566 if (tmp & PORT_CS_PORT_RST)
567 printf("Err: Failed to clear port RST\n");
568 }
569
570
571 for (cnt = 0; cnt < 100; cnt++) {
572 tmp = readl(port + PORT_SSTATUS);
573 if ((tmp & 0xF) == 0x3)
574 break;
575 mdelay(1);
576 }
577
578 tmp = readl(port + PORT_SSTATUS);
579 if ((tmp & 0xf) != 0x3) {
580 printf(" (No RDY)\n");
581 return 1;
582 }
583
584
585 tmp = ata_wait_register(port + PORT_CTRL_STAT,
586 PORT_CS_RDY, PORT_CS_RDY, 100);
587 if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
588 printf("%d port not ready.\n", dev);
589 return 1;
590 }
591
592
593 sil_config_port(port);
594
595
596 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
597 readl(port + PORT_CTRL_STAT);
598 tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
599 PORT_CS_DEV_RST, 100);
600 if (tmp & PORT_CS_DEV_RST) {
601 printf("%d port reset failed.\n", dev);
602 return 1;
603 }
604
605 sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
606 if (!sata) {
607 printf("%d no memory.\n", dev);
608 return 1;
609 }
610 memset((void *)sata, 0, sizeof(struct sil_sata));
611
612
613#if !CONFIG_IS_ENABLED(BLK)
614 sata_dev_desc[dev].priv = (void *)sata;
615 sata->devno = sata_info.devno;
616#else
617 priv->sil_sata_desc[dev] = sata;
618 priv->port_num = dev;
619#ifdef CONFIG_DM_PCI
620 sata->devno = uc_dev->parent;
621#else
622 sata->devno = sata_info.devno;
623#endif
624#endif
625 sata->id = dev;
626 sata->port = port;
627 sprintf(sata->name, "SATA#%d", dev);
628 sil_cmd_soft_reset(sata);
629 tmp = readl(port + PORT_SSTATUS);
630 tmp = (tmp >> 4) & 0xf;
631 printf(" (%s)\n", sata_spd_string(tmp));
632
633 return 0;
634}
635
636#if !CONFIG_IS_ENABLED(BLK)
637
638
639
640int init_sata(int dev)
641{
642 static int init_done, idx;
643 pci_dev_t devno;
644 u16 word;
645
646 if (init_done == 1 && dev < sata_info.maxport)
647 goto init_start;
648
649 init_done = 1;
650
651
652 devno = pci_find_devices(supported, idx++);
653 if (devno == -1)
654 return 1;
655
656 pci_read_config_word(devno, PCI_DEVICE_ID, &word);
657
658
659 word &= 0xf;
660
661 sata_info.portbase = 0;
662 sata_info.maxport = sata_info.portbase + word;
663 sata_info.devno = devno;
664
665
666 sata_info.iobase[0] = (ulong)pci_map_bar(devno,
667 PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
668 sata_info.iobase[1] = (ulong)pci_map_bar(devno,
669 PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
670
671
672 sata_info.iobase[0] &= 0xffffff80;
673 sata_info.iobase[1] &= 0xfffffc00;
674
675
676 pci_write_config_word(devno, PCI_COMMAND,
677 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
678
679
680 pci_read_config_word(devno, PCI_COMMAND, &word);
681 if (!(word & PCI_COMMAND_MEMORY) ||
682 (!(word & PCI_COMMAND_MASTER))) {
683 printf("Error: Can not enable MEM access or Bus Mastering.\n");
684 debug("PCI command: %04x\n", word);
685 return 1;
686 }
687
688
689 writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
690
691 writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
692
693init_start:
694 return sil_init_sata(dev);
695}
696
697int reset_sata(int dev)
698{
699 return 0;
700}
701
702
703
704
705int scan_sata(int dev)
706{
707 struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
708#else
709static int scan_sata(struct udevice *blk_dev, int dev)
710{
711 struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
712 struct sil_sata_priv *priv = dev_get_plat(blk_dev);
713 struct sil_sata *sata = priv->sil_sata_desc[dev];
714#endif
715 unsigned char serial[ATA_ID_SERNO_LEN + 1];
716 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
717 unsigned char product[ATA_ID_PROD_LEN + 1];
718 u16 *id;
719
720 id = (u16 *)malloc(ATA_ID_WORDS * 2);
721 if (!id) {
722 printf("Id malloc failed\n");
723 return 1;
724 }
725 sil_cmd_identify_device(sata, id);
726
727 sil_sata_set_feature_by_id(sata, id);
728
729
730 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
731
732
733 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
734
735
736 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
737
738#if !CONFIG_IS_ENABLED(BLK)
739 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
740 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
741 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
742
743 sata_dev_desc[dev].lba = ata_id_n_sectors(id);
744#ifdef CONFIG_LBA48
745 sata_dev_desc[dev].lba48 = sata->lba48;
746#endif
747#else
748 memcpy(desc->product, serial, sizeof(serial));
749 memcpy(desc->revision, firmware, sizeof(firmware));
750 memcpy(desc->vendor, product, sizeof(product));
751 desc->lba = ata_id_n_sectors(id);
752#ifdef CONFIG_LBA48
753 desc->lba48 = sata->lba48;
754#endif
755#endif
756
757#ifdef DEBUG
758 ata_dump_id(id);
759#endif
760 free((void *)id);
761
762 return 0;
763}
764
765#if CONFIG_IS_ENABLED(BLK)
766static const struct blk_ops sata_sil_blk_ops = {
767 .read = sata_read,
768 .write = sata_write,
769};
770
771U_BOOT_DRIVER(sata_sil_driver) = {
772 .name = "sata_sil_blk",
773 .id = UCLASS_BLK,
774 .ops = &sata_sil_blk_ops,
775 .plat_auto = sizeof(struct sil_sata_priv),
776};
777
778static int sil_unbind_device(struct udevice *dev)
779{
780 int ret;
781
782 ret = device_remove(dev, DM_REMOVE_NORMAL);
783 if (ret)
784 return ret;
785
786 ret = device_unbind(dev);
787 if (ret)
788 return ret;
789
790 return 0;
791}
792
793static int sil_pci_probe(struct udevice *dev)
794{
795 struct udevice *blk;
796 int failed_number;
797 char sata_name[10];
798 pci_dev_t devno;
799 u16 word;
800 int ret;
801 int i;
802
803 failed_number = 0;
804
805
806 devno = dm_pci_get_bdf(dev);
807 if (devno == -1)
808 return 1;
809
810 dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
811
812
813 word &= 0xf;
814
815 sata_info.portbase = 0;
816 sata_info.maxport = sata_info.portbase + word;
817 sata_info.devno = devno;
818
819
820 sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
821 PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
822 sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
823 PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
824
825
826 sata_info.iobase[0] &= 0xffffff80;
827 sata_info.iobase[1] &= 0xfffffc00;
828
829
830 dm_pci_write_config16(dev, PCI_COMMAND,
831 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
832
833
834 dm_pci_read_config16(dev, PCI_COMMAND, &word);
835 if (!(word & PCI_COMMAND_MEMORY) ||
836 (!(word & PCI_COMMAND_MASTER))) {
837 printf("Error: Can not enable MEM access or Bus Mastering.\n");
838 debug("PCI command: %04x\n", word);
839 return 1;
840 }
841
842
843 writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
844
845 writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
846
847 for (i = sata_info.portbase; i < sata_info.maxport; i++) {
848 snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
849 ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
850 IF_TYPE_SATA, -1, 512, 0, &blk);
851 if (ret) {
852 debug("Can't create device\n");
853 return ret;
854 }
855
856 ret = sil_init_sata(blk, i);
857 if (ret) {
858 ret = sil_unbind_device(blk);
859 if (ret)
860 return ret;
861
862 failed_number++;
863 continue;
864 }
865
866 ret = scan_sata(blk, i);
867 if (ret) {
868 ret = sil_unbind_device(blk);
869 if (ret)
870 return ret;
871
872 failed_number++;
873 continue;
874 }
875 }
876
877 if (failed_number == sata_info.maxport)
878 return -ENODEV;
879 else
880 return 0;
881}
882
883static int sil_pci_remove(struct udevice *dev)
884{
885 int i;
886 struct sil_sata *sata;
887 struct sil_sata_priv *priv;
888
889 priv = dev_get_priv(dev);
890
891 for (i = sata_info.portbase; i < sata_info.maxport; i++) {
892 sata = priv->sil_sata_desc[i];
893 if (sata)
894 free(sata);
895 }
896
897 return 0;
898}
899
900static int sata_sil_scan(struct udevice *dev)
901{
902
903
904 return 0;
905}
906
907struct sil_ops sata_sil_ops = {
908 .scan = sata_sil_scan,
909};
910
911static const struct udevice_id sil_pci_ids[] = {
912 { .compatible = "sil-pci-sample" },
913 { }
914};
915
916U_BOOT_DRIVER(sil_ahci_pci) = {
917 .name = "sil_ahci_pci",
918 .id = UCLASS_AHCI,
919 .of_match = sil_pci_ids,
920 .ops = &sata_sil_ops,
921 .probe = sil_pci_probe,
922 .remove = sil_pci_remove,
923 .priv_auto = sizeof(struct sil_sata_priv),
924};
925
926U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
927#endif
928
