1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Motorola MC5282EVB board. 4 * 5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef _CONFIG_M5282EVB_H 13#define _CONFIG_M5282EVB_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19#define CONFIG_MCFTMR 20 21#define CONFIG_MCFUART 22#define CONFIG_SYS_UART_PORT (0) 23 24#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 25 26/* Configuration for environment 27 * Environment is embedded in u-boot in the second sector of the flash 28 */ 29 30#define LDS_BOARD_TEXT \ 31 . = DEFINED(env_offset) ? env_offset : .; \ 32 env/embedded.o(.text*); 33 34/* 35 * BOOTP options 36 */ 37#define CONFIG_BOOTP_BOOTFILESIZE 38 39#ifdef CONFIG_MCFFEC 40# define CONFIG_MII_INIT 1 41# define CONFIG_SYS_DISCOVER_PHY 42# define CONFIG_SYS_RX_ETH_BUFFER 8 43# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 44/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 45# ifndef CONFIG_SYS_DISCOVER_PHY 46# define FECDUPLEX FULL 47# define FECSPEED _100BASET 48# else 49# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 50# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 51# endif 52# endif /* CONFIG_SYS_DISCOVER_PHY */ 53#endif 54 55#ifdef CONFIG_MCFFEC 56# define CONFIG_IPADDR 192.162.1.2 57# define CONFIG_NETMASK 255.255.255.0 58# define CONFIG_SERVERIP 192.162.1.1 59# define CONFIG_GATEWAYIP 192.162.1.1 60#endif /* CONFIG_MCFFEC */ 61 62#define CONFIG_HOSTNAME "M5282EVB" 63#define CONFIG_EXTRA_ENV_SETTINGS \ 64 "netdev=eth0\0" \ 65 "loadaddr=10000\0" \ 66 "u-boot=u-boot.bin\0" \ 67 "load=tftp ${loadaddr) ${u-boot}\0" \ 68 "upd=run load; run prog\0" \ 69 "prog=prot off ffe00000 ffe3ffff;" \ 70 "era ffe00000 ffe3ffff;" \ 71 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 72 "save\0" \ 73 "" 74 75#define CONFIG_SYS_LOAD_ADDR 0x20000 76 77#define CONFIG_SYS_CLK 64000000 78 79/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 80 81#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 82#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 83 84/* 85 * Low Level Configuration Settings 86 * (address mappings, register initial values, etc.) 87 * You should know what you are doing if you make changes here. 88 */ 89#define CONFIG_SYS_MBAR 0x40000000 90 91/*----------------------------------------------------------------------- 92 * Definitions for initial stack pointer and data area (in DPRAM) 93 */ 94#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 95#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 96#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 97#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 98 99/*----------------------------------------------------------------------- 100 * Start addresses for the final memory configuration 101 * (Set up by the startup code) 102 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 103 */ 104#define CONFIG_SYS_SDRAM_BASE 0x00000000 105#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 106#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 107#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 108#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 109 110/* If M5282 port is fully implemented the monitor base will be behind 111 * the vector table. */ 112#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 113#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 114#else 115#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 116#endif 117 118#define CONFIG_SYS_MONITOR_LEN 0x20000 119#define CONFIG_SYS_MALLOC_LEN (256 << 10) 120#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 121 122/* 123 * For booting Linux, the board info and command line data 124 * have to be in the first 8 MB of memory, since this is 125 * the maximum mapped by the Linux kernel during initialization ?? 126 */ 127#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 128 129/*----------------------------------------------------------------------- 130 * FLASH organization 131 */ 132#ifdef CONFIG_SYS_FLASH_CFI 133 134# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 135# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 136# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 137# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 138# define CONFIG_SYS_FLASH_CHECKSUM 139# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 140#endif 141 142/*----------------------------------------------------------------------- 143 * Cache Configuration 144 */ 145#define CONFIG_SYS_CACHELINE_SIZE 16 146 147#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 148 CONFIG_SYS_INIT_RAM_SIZE - 8) 149#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 150 CONFIG_SYS_INIT_RAM_SIZE - 4) 151#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 152#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 153 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 154 CF_ACR_EN | CF_ACR_SM_ALL) 155#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 156 CF_CACR_CEIB | CF_CACR_DBWE | \ 157 CF_CACR_EUSP) 158 159/*----------------------------------------------------------------------- 160 * Memory bank definitions 161 */ 162#define CONFIG_SYS_CS0_BASE 0xFFE00000 163#define CONFIG_SYS_CS0_CTRL 0x00001980 164#define CONFIG_SYS_CS0_MASK 0x001F0001 165 166/*----------------------------------------------------------------------- 167 * Port configuration 168 */ 169#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 170#define CONFIG_SYS_PADDR 0x0000000 171#define CONFIG_SYS_PADAT 0x0000000 172 173#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 174#define CONFIG_SYS_PBDDR 0x0000000 175#define CONFIG_SYS_PBDAT 0x0000000 176 177#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 178#define CONFIG_SYS_PCDDR 0x0000000 179#define CONFIG_SYS_PCDAT 0x0000000 180 181#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 182#define CONFIG_SYS_PCDDR 0x0000000 183#define CONFIG_SYS_PCDAT 0x0000000 184 185#define CONFIG_SYS_PEHLPAR 0xC0 186#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 187#define CONFIG_SYS_DDRUA 0x05 188#define CONFIG_SYS_PJPAR 0xFF 189 190#endif /* _CONFIG_M5282EVB_H */ 191