1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF54418 TWR board. 4 * 5 * Copyright 2010-2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M54418TWR_H 14#define _M54418TWR_H 15 16#include <linux/stringify.h> 17 18/* 19 * High Level Configuration Options 20 * (easy to change) 21 */ 22 23#define CONFIG_MCFUART 24#define CONFIG_SYS_UART_PORT (0) 25#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 26 27#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*) 28 29#undef CONFIG_WATCHDOG 30 31#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33/* 34 * BOOTP options 35 */ 36#define CONFIG_BOOTP_BOOTFILESIZE 37 38/* 39 * NAND FLASH 40 */ 41#ifdef CONFIG_CMD_NAND 42#define CONFIG_JFFS2_NAND 43#define CONFIG_NAND_FSL_NFC 44#define CONFIG_SYS_NAND_BASE 0xFC0FC000 45#define CONFIG_SYS_MAX_NAND_DEVICE 1 46#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 47#define CONFIG_SYS_NAND_SELECT_DEVICE 48#endif 49 50/* Network configuration */ 51#ifdef CONFIG_MCFFEC 52#define CONFIG_MII_INIT 1 53#define CONFIG_SYS_DISCOVER_PHY 54#define CONFIG_SYS_RX_ETH_BUFFER 2 55#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56#define CONFIG_SYS_TX_ETH_BUFFER 2 57#define CONFIG_HAS_ETH1 58 59#define CONFIG_ETHPRIME "FEC0" 60#define CONFIG_IPADDR 192.168.1.2 61#define CONFIG_NETMASK 255.255.255.0 62#define CONFIG_SERVERIP 192.168.1.1 63#define CONFIG_GATEWAYIP 192.168.1.1 64 65#define CONFIG_SYS_FEC_BUF_USE_SRAM 66/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 67#ifndef CONFIG_SYS_DISCOVER_PHY 68#define FECDUPLEX FULL 69#define FECSPEED _100BASET 70#define LINKSTATUS 1 71#else 72#define LINKSTATUS 0 73#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75#endif 76#endif /* CONFIG_SYS_DISCOVER_PHY */ 77#endif 78 79#define CONFIG_HOSTNAME "M54418TWR" 80 81#if defined(CONFIG_CF_SBF) 82/* ST Micro serial flash */ 83#define CONFIG_SYS_LOAD_ADDR2 0x40010007 84#define CONFIG_EXTRA_ENV_SETTINGS \ 85 "netdev=eth0\0" \ 86 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 87 "loadaddr=0x40010000\0" \ 88 "sbfhdr=sbfhdr.bin\0" \ 89 "uboot=u-boot.bin\0" \ 90 "load=tftp ${loadaddr} ${sbfhdr};" \ 91 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 92 "upd=run load; run prog\0" \ 93 "prog=sf probe 0:1 1000000 3;" \ 94 "sf erase 0 40000;" \ 95 "sf write ${loadaddr} 0 40000;" \ 96 "save\0" \ 97 "" 98#elif defined(CONFIG_SYS_NAND_BOOT) 99#define CONFIG_EXTRA_ENV_SETTINGS \ 100 "netdev=eth0\0" \ 101 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 102 "loadaddr=0x40010000\0" \ 103 "u-boot=u-boot.bin\0" \ 104 "load=tftp ${loadaddr} ${u-boot};\0" \ 105 "upd=run load; run prog\0" \ 106 "prog=nand device 0;" \ 107 "nand erase 0 40000;" \ 108 "nb_update ${loadaddr} ${filesize};" \ 109 "save\0" \ 110 "" 111#else 112#define CONFIG_SYS_UBOOT_END 0x3FFFF 113#define CONFIG_EXTRA_ENV_SETTINGS \ 114 "netdev=eth0\0" \ 115 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 116 "loadaddr=40010000\0" \ 117 "u-boot=u-boot.bin\0" \ 118 "load=tftp ${loadaddr) ${u-boot}\0" \ 119 "upd=run load; run prog\0" \ 120 "prog=prot off mram" " ;" \ 121 "cp.b ${loadaddr} 0 ${filesize};" \ 122 "save\0" \ 123 "" 124#endif 125 126/* Realtime clock */ 127#undef CONFIG_MCFRTC 128#define CONFIG_RTC_MCFRRTC 129#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 130 131/* Timer */ 132#define CONFIG_MCFTMR 133 134/* I2c */ 135#undef CONFIG_SYS_FSL_I2C 136#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 137/* I2C speed and slave address */ 138#define CONFIG_SYS_I2C_SPEED 80000 139#define CONFIG_SYS_I2C_SLAVE 0x7F 140#define CONFIG_SYS_I2C_OFFSET 0x58000 141#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 142 143/* DSPI and Serial Flash */ 144#define CONFIG_CF_DSPI 145#define CONFIG_SERIAL_FLASH 146#define CONFIG_SYS_SBFHDR_SIZE 0x7 147 148/* Input, PCI, Flexbus, and VCO */ 149#define CONFIG_EXTRA_CLOCK 150 151#define CONFIG_PRAM 2048 /* 2048 KB */ 152 153#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 154 155#define CONFIG_SYS_MBAR 0xFC000000 156 157/* 158 * Low Level Configuration Settings 159 * (address mappings, register initial values, etc.) 160 * You should know what you are doing if you make changes here. 161 */ 162 163/*----------------------------------------------------------------------- 164 * Definitions for initial stack pointer and data area (in DPRAM) 165 */ 166#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 167/* End of used area in internal SRAM */ 168#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 169#define CONFIG_SYS_INIT_RAM_CTRL 0x221 170#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 171 GENERATED_GBL_DATA_SIZE) - 32) 172#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 173#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 174 175/*----------------------------------------------------------------------- 176 * Start addresses for the final memory configuration 177 * (Set up by the startup code) 178 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 179 */ 180#define CONFIG_SYS_SDRAM_BASE 0x40000000 181#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 182 183#define CONFIG_SYS_DRAM_TEST 184 185#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 186#define CONFIG_SERIAL_BOOT 187#endif 188 189#if defined(CONFIG_SERIAL_BOOT) 190#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 191#else 192#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 193#endif 194 195#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 196/* Reserve 256 kB for Monitor */ 197#define CONFIG_SYS_MONITOR_LEN (256 << 10) 198/* Reserve 256 kB for malloc() */ 199#define CONFIG_SYS_MALLOC_LEN (256 << 10) 200 201/* 202 * For booting Linux, the board info and command line data 203 * have to be in the first 8 MB of memory, since this is 204 * the maximum mapped by the Linux kernel during initialization ?? 205 */ 206/* Initial Memory map for Linux */ 207#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 208 (CONFIG_SYS_SDRAM_SIZE << 20)) 209 210/* Configuration for environment 211 * Environment is embedded in u-boot in the second sector of the flash 212 */ 213 214/* FLASH organization */ 215#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 216 217#ifdef CONFIG_SYS_FLASH_CFI 218 219/* Max size that the board might have */ 220#define CONFIG_SYS_FLASH_SIZE 0x1000000 221#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 222/* max number of memory banks */ 223#define CONFIG_SYS_MAX_FLASH_BANKS 1 224/* max number of sectors on one chip */ 225#define CONFIG_SYS_MAX_FLASH_SECT 270 226/* "Real" (hardware) sectors protection */ 227#define CONFIG_SYS_FLASH_CHECKSUM 228#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 229#else 230/* max number of sectors on one chip */ 231#define CONFIG_SYS_MAX_FLASH_SECT 270 232/* max number of sectors on one chip */ 233#define CONFIG_SYS_MAX_FLASH_BANKS 0 234#endif 235 236/* 237 * This is setting for JFFS2 support in u-boot. 238 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 239 */ 240#ifdef CONFIG_CMD_JFFS2 241#define CONFIG_JFFS2_DEV "nand0" 242#define CONFIG_JFFS2_PART_OFFSET (0x800000) 243 244#endif 245 246/* Cache Configuration */ 247#define CONFIG_SYS_CACHELINE_SIZE 16 248#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 249 CONFIG_SYS_INIT_RAM_SIZE - 8) 250#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 251 CONFIG_SYS_INIT_RAM_SIZE - 4) 252#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 253#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 254#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 255 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 256 CF_ACR_EN | CF_ACR_SM_ALL) 257#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 258 CF_CACR_ICINVA | CF_CACR_EUSP) 259#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 260 CF_CACR_DEC | CF_CACR_DDCM_P | \ 261 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 262 263#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 264 CONFIG_SYS_INIT_RAM_SIZE - 12) 265 266/*----------------------------------------------------------------------- 267 * Memory bank definitions 268 */ 269/* 270 * CS0 - NOR Flash 16MB 271 * CS1 - Available 272 * CS2 - Available 273 * CS3 - Available 274 * CS4 - Available 275 * CS5 - Available 276 */ 277 278 /* Flash */ 279#define CONFIG_SYS_CS0_BASE 0x00000000 280#define CONFIG_SYS_CS0_MASK 0x000F0101 281#define CONFIG_SYS_CS0_CTRL 0x00001D60 282 283#endif /* _M54418TWR_H */ 284