LXR uboot/include/configs/MPC8349EMDS

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2006-2010
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 */
   6
   7/*
   8 * mpc8349emds board configuration file
   9 *
  10 */
  11
  12#ifndef __CONFIG_H
  13#define __CONFIG_H
  14
  15/*
  16 * High Level Configuration Options
  17 */
  18#define CONFIG_E300             1       /* E300 Family */
  19
  20#undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  21
  22/*
  23 * DDR Setup
  24 */
  25#define CONFIG_DDR_ECC                  /* support DDR ECC function */
  26#define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  27#define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  28
  29/*
  30 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  31 * unselect it to use old spd_sdram.c
  32 */
  33#define CONFIG_SYS_SPD_BUS_NUM  0
  34#define SPD_EEPROM_ADDRESS1     0x52
  35#define SPD_EEPROM_ADDRESS2     0x51
  36#define CONFIG_DIMM_SLOTS_PER_CTLR      2
  37#define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  38#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  39#define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  40
  41/*
  42 * 32-bit data path mode.
  43 *
  44 * Please note that using this mode for devices with the real density of 64-bit
  45 * effectively reduces the amount of available memory due to the effect of
  46 * wrapping around while translating address to row/columns, for example in the
  47 * 256MB module the upper 128MB get aliased with contents of the lower
  48 * 128MB); normally this define should be used for devices with real 32-bit
  49 * data path.
  50 */
  51#undef CONFIG_DDR_32BIT
  52
  53#define CONFIG_SYS_SDRAM_BASE   0x00000000      /* DDR is system memory*/
  54#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  55                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  56#undef  CONFIG_DDR_2T_TIMING
  57
  58/*
  59 * DDRCDR - DDR Control Driver Register
  60 */
  61#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  62
  63#if defined(CONFIG_SPD_EEPROM)
  64/*
  65 * Determine DDR configuration from I2C interface.
  66 */
  67#define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  68#else
  69/*
  70 * Manually set up DDR parameters
  71 */
  72#define CONFIG_SYS_DDR_SIZE             256             /* MB */
  73#if defined(CONFIG_DDR_II)
  74#define CONFIG_SYS_DDRCDR               0x80080001
  75#define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
  76#define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
  77#define CONFIG_SYS_DDR_TIMING_0         0x00220802
  78#define CONFIG_SYS_DDR_TIMING_1         0x38357322
  79#define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
  80#define CONFIG_SYS_DDR_TIMING_3         0x00000000
  81#define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
  82#define CONFIG_SYS_DDR_MODE             0x47d00432
  83#define CONFIG_SYS_DDR_MODE2            0x8000c000
  84#define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
  85#define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
  86#define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  87#else
  88#define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  89                                | CSCONFIG_ROW_BIT_13 \
  90                                | CSCONFIG_COL_BIT_10)
  91#define CONFIG_SYS_DDR_TIMING_1 0x36332321
  92#define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  93#define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
  94#define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
  95
  96#if defined(CONFIG_DDR_32BIT)
  97/* set burst length to 8 for 32-bit data path */
  98                                /* DLL,normal,seq,4/2.5, 8 burst len */
  99#define CONFIG_SYS_DDR_MODE     0x00000023
 100#else
 101/* the default burst length is 4 - for 64-bit data path */
 102                                /* DLL,normal,seq,4/2.5, 4 burst len */
 103#define CONFIG_SYS_DDR_MODE     0x00000022
 104#endif
 105#endif
 106#endif
 107
 108/*
 109 * SDRAM on the Local Bus
 110 */
 111#define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 112#define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 113
 114/*
 115 * FLASH on the Local Bus
 116 */
 117#define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 118#define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 119
 120#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 121#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 122
 123#undef CONFIG_SYS_FLASH_CHECKSUM
 124#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 125#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 126
 127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 128
 129#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 130#define CONFIG_SYS_RAMBOOT
 131#else
 132#undef  CONFIG_SYS_RAMBOOT
 133#endif
 134
 135/*
 136 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 137 */
 138#define CONFIG_SYS_BCSR                 0xE2400000
 139                                        /* Access window base at BCSR base */
 140#define CONFIG_SYS_INIT_RAM_LOCK        1
 141#define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 142#define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 143
 144#define CONFIG_SYS_GBL_DATA_OFFSET      \
 145                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 146#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 147
 148#define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 149#define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 150
 151/*
 152 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 153 */
 154
 155/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 156/*
 157 * Base Register 2 and Option Register 2 configure SDRAM.
 158 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 159 *
 160 * For BR2, need:
 161 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 162 *    port-size = 32-bits = BR2[19:20] = 11
 163 *    no parity checking = BR2[21:22] = 00
 164 *    SDRAM for MSEL = BR2[24:26] = 011
 165 *    Valid = BR[31] = 1
 166 *
 167 * 0    4    8    12   16   20   24   28
 168 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 169 */
 170
 171/*
 172 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 173 *
 174 * For OR2, need:
 175 *    64MB mask for AM, OR2[0:7] = 1111 1100
 176 *                 XAM, OR2[17:18] = 11
 177 *    9 columns OR2[19-21] = 010
 178 *    13 rows   OR2[23-25] = 100
 179 *    EAD set for extra time OR[31] = 1
 180 *
 181 * 0    4    8    12   16   20   24   28
 182 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 183 */
 184
 185
 186                                /* LB sdram refresh timer, about 6us */
 187#define CONFIG_SYS_LBC_LSRT     0x32000000
 188                                /* LB refresh timer prescal, 266MHz/32 */
 189#define CONFIG_SYS_LBC_MRTPR    0x20000000
 190
 191#define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN      \
 192                                | LSDMR_BSMA1516        \
 193                                | LSDMR_RFCR8           \
 194                                | LSDMR_PRETOACT6       \
 195                                | LSDMR_ACTTORW3        \
 196                                | LSDMR_BL8             \
 197                                | LSDMR_WRC3            \
 198                                | LSDMR_CL3)
 199
 200/*
 201 * SDRAM Controller configuration sequence.
 202 */
 203#define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 204#define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 205#define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 206#define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 207#define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 208
 209/*
 210 * Serial Port
 211 */
 212#define CONFIG_SYS_NS16550_SERIAL
 213#define CONFIG_SYS_NS16550_REG_SIZE    1
 214#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 215
 216#define CONFIG_SYS_BAUDRATE_TABLE  \
 217                {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 218
 219#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 220#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 221
 222/* I2C */
 223#define CONFIG_SYS_I2C
 224#define CONFIG_SYS_I2C_FSL
 225#define CONFIG_SYS_FSL_I2C_SPEED        400000
 226#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 227#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 228#define CONFIG_SYS_FSL_I2C2_SPEED       400000
 229#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 230#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 231#define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 232
 233/* SPI */
 234#undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 235
 236/* GPIOs.  Used as SPI chip selects */
 237#define CONFIG_SYS_GPIO1_PRELIM
 238#define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 239#define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 240
 241/* TSEC */
 242#define CONFIG_SYS_TSEC1_OFFSET 0x24000
 243#define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 244#define CONFIG_SYS_TSEC2_OFFSET 0x25000
 245#define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 246
 247/* USB */
 248#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 249
 250/*
 251 * General PCI
 252 * Addresses are mapped 1-1.
 253 */
 254#define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 255#define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 256#define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 257#define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 258#define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 259#define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 260#define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 261#define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 262#define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 263
 264#define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 265#define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 266#define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 267#define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 268#define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 269#define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 270#define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 271#define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 272#define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 273
 274#if defined(CONFIG_PCI)
 275
 276#define CONFIG_83XX_PCI_STREAMING
 277
 278
 279#if !defined(CONFIG_PCI_PNP)
 280        #define PCI_ENET0_IOADDR        0xFIXME
 281        #define PCI_ENET0_MEMADDR       0xFIXME
 282        #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 283#endif
 284
 285#undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 286#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 287
 288#endif  /* CONFIG_PCI */
 289
 290/*
 291 * TSEC configuration
 292 */
 293
 294#if defined(CONFIG_TSEC_ENET)
 295
 296#define CONFIG_GMII             1       /* MII PHY management */
 297#define CONFIG_TSEC1            1
 298#define CONFIG_TSEC1_NAME       "TSEC0"
 299#define CONFIG_TSEC2            1
 300#define CONFIG_TSEC2_NAME       "TSEC1"
 301#define TSEC1_PHY_ADDR          0
 302#define TSEC2_PHY_ADDR          1
 303#define TSEC1_PHYIDX            0
 304#define TSEC2_PHYIDX            0
 305#define TSEC1_FLAGS             TSEC_GIGABIT
 306#define TSEC2_FLAGS             TSEC_GIGABIT
 307
 308/* Options are: TSEC[0-1] */
 309#define CONFIG_ETHPRIME         "TSEC0"
 310
 311#endif  /* CONFIG_TSEC_ENET */
 312
 313/*
 314 * Configure on-board RTC
 315 */
 316#define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 317#define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 318
 319/*
 320 * Environment
 321 */
 322#ifndef CONFIG_SYS_RAMBOOT
 323/* Address and size of Redundant Environment Sector     */
 324#endif
 325
 326#define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 327#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 328
 329/*
 330 * BOOTP options
 331 */
 332#define CONFIG_BOOTP_BOOTFILESIZE
 333
 334#undef CONFIG_WATCHDOG                  /* watchdog disabled */
 335
 336/*
 337 * Miscellaneous configurable options
 338 */
 339#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 340
 341/*
 342 * For booting Linux, the board info and command line data
 343 * have to be in the first 256 MB of memory, since this is
 344 * the maximum mapped by the Linux kernel during initialization.
 345 */
 346                                /* Initial Memory map for Linux*/
 347#define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 348#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 349
 350#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 351
 352/*
 353 * System performance
 354 */
 355#define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 356#define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 357#define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 358#define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 359
 360/* System IO Config */
 361#define CONFIG_SYS_SICRH 0
 362#define CONFIG_SYS_SICRL SICRL_LDP_A
 363
 364#ifdef CONFIG_PCI
 365#define CONFIG_PCI_INDIRECT_BRIDGE
 366#endif
 367
 368#if defined(CONFIG_CMD_KGDB)
 369#define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 370#endif
 371
 372/*
 373 * Environment Configuration
 374 */
 375
 376#if defined(CONFIG_TSEC_ENET)
 377#define CONFIG_HAS_ETH1
 378#define CONFIG_HAS_ETH0
 379#endif
 380
 381#define CONFIG_HOSTNAME         "mpc8349emds"
 382#define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 383#define CONFIG_BOOTFILE         "uImage"
 384
 385#define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 386
 387#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 388        "netdev=eth0\0"                                                 \
 389        "hostname=mpc8349emds\0"                                        \
 390        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 391                "nfsroot=${serverip}:${rootpath}\0"                     \
 392        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 393        "addip=setenv bootargs ${bootargs} "                            \
 394                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 395                ":${hostname}:${netdev}:off panic=1\0"                  \
 396        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 397        "flash_nfs=run nfsargs addip addtty;"                           \
 398                "bootm ${kernel_addr}\0"                                \
 399        "flash_self=run ramargs addip addtty;"                          \
 400                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 401        "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 402                "bootm\0"                                               \
 403        "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 404        "update=protect off fe000000 fe03ffff; "                        \
 405                "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 406        "upd=run load update\0"                                         \
 407        "fdtaddr=780000\0"                                              \
 408        "fdtfile=mpc834x_mds.dtb\0"                                     \
 409        ""
 410
 411#define CONFIG_NFSBOOTCOMMAND                                           \
 412        "setenv bootargs root=/dev/nfs rw "                             \
 413                "nfsroot=$serverip:$rootpath "                          \
 414                "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 415                                                        "$netdev:off "  \
 416                "console=$consoledev,$baudrate $othbootargs;"           \
 417        "tftp $loadaddr $bootfile;"                                     \
 418        "tftp $fdtaddr $fdtfile;"                                       \
 419        "bootm $loadaddr - $fdtaddr"
 420
 421#define CONFIG_RAMBOOTCOMMAND                                           \
 422        "setenv bootargs root=/dev/ram rw "                             \
 423                "console=$consoledev,$baudrate $othbootargs;"           \
 424        "tftp $ramdiskaddr $ramdiskfile;"                               \
 425        "tftp $loadaddr $bootfile;"                                     \
 426        "tftp $fdtaddr $fdtfile;"                                       \
 427        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 428
 429#define CONFIG_BOOTCOMMAND      "run flash_self"
 430
 431#endif  /* __CONFIG_H */
 432