1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * 7 * Configuation settings for the AT91SAM9263EK board. 8 */ 9 10#ifndef __CONFIG_H 11#define __CONFIG_H 12 13#include <linux/stringify.h> 14 15/* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19#include <asm/hardware.h> 20 21/* ARM asynchronous clock */ 22#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 23#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 24 25#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 26#define CONFIG_SETUP_MEMORY_TAGS 1 27#define CONFIG_INITRD_TAG 1 28 29#ifndef CONFIG_SYS_USE_BOOT_NORFLASH 30#define CONFIG_SKIP_LOWLEVEL_INIT 31#else 32#define CONFIG_SYS_USE_NORFLASH 33#endif 34 35/* 36 * Hardware drivers 37 */ 38#define CONFIG_ATMEL_LEGACY 39 40/* LCD */ 41#define LCD_BPP LCD_COLOR8 42#define CONFIG_LCD_LOGO 1 43#undef LCD_TEST_PATTERN 44#define CONFIG_LCD_INFO 1 45#define CONFIG_LCD_INFO_BELOW_LOGO 1 46#define CONFIG_ATMEL_LCD 1 47#define CONFIG_ATMEL_LCD_BGR555 1 48 49/* 50 * BOOTP options 51 */ 52#define CONFIG_BOOTP_BOOTFILESIZE 1 53 54/* SDRAM */ 55#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 56#define CONFIG_SYS_SDRAM_SIZE 0x04000000 57 58#define CONFIG_SYS_INIT_SP_ADDR \ 59 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 60 61/* NOR flash, if populated */ 62#ifdef CONFIG_SYS_USE_NORFLASH 63#define PHYS_FLASH_1 0x10000000 64#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 65#define CONFIG_SYS_MAX_FLASH_SECT 256 66#define CONFIG_SYS_MAX_FLASH_BANKS 1 67 68#define CONFIG_SYS_MONITOR_SEC 1:0-3 69#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 70#define CONFIG_SYS_MONITOR_LEN (256 << 10) 71 72/* Address and size of Primary Environment Sector */ 73 74#define CONFIG_EXTRA_ENV_SETTINGS \ 75 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 76 "update=" \ 77 "protect off ${monitor_base} +${filesize};" \ 78 "erase ${monitor_base} +${filesize};" \ 79 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 80 "protect on ${monitor_base} +${filesize}\0" 81 82#ifndef CONFIG_SKIP_LOWLEVEL_INIT 83#define MASTER_PLL_MUL 171 84#define MASTER_PLL_DIV 14 85#define MASTER_PLL_OUT 3 86 87/* clocks */ 88#define CONFIG_SYS_MOR_VAL \ 89 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 90#define CONFIG_SYS_PLLAR_VAL \ 91 (AT91_PMC_PLLAR_29 | \ 92 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 93 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 94 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 95 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 96 97/* PCK/2 = MCK Master Clock from PLLA */ 98#define CONFIG_SYS_MCKR1_VAL \ 99 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 100 AT91_PMC_MCKR_MDIV_2) 101 102/* PCK/2 = MCK Master Clock from PLLA */ 103#define CONFIG_SYS_MCKR2_VAL \ 104 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 105 AT91_PMC_MCKR_MDIV_2) 106 107/* define PDC[31:16] as DATA[31:16] */ 108#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 109/* no pull-up for D[31:16] */ 110#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 111/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 112#define CONFIG_SYS_MATRIX_EBICSA_VAL \ 113 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 114 AT91_MATRIX_CSA_EBI_CS1A) 115 116/* SDRAM */ 117/* SDRAMC_MR Mode register */ 118#define CONFIG_SYS_SDRC_MR_VAL1 0 119/* SDRAMC_TR - Refresh Timer register */ 120#define CONFIG_SYS_SDRC_TR_VAL1 0x13C 121/* SDRAMC_CR - Configuration register*/ 122#define CONFIG_SYS_SDRC_CR_VAL \ 123 (AT91_SDRAMC_NC_9 | \ 124 AT91_SDRAMC_NR_13 | \ 125 AT91_SDRAMC_NB_4 | \ 126 AT91_SDRAMC_CAS_3 | \ 127 AT91_SDRAMC_DBW_32 | \ 128 (1 << 8) | /* Write Recovery Delay */ \ 129 (7 << 12) | /* Row Cycle Delay */ \ 130 (2 << 16) | /* Row Precharge Delay */ \ 131 (2 << 20) | /* Row to Column Delay */ \ 132 (5 << 24) | /* Active to Precharge Delay */ \ 133 (1 << 28)) /* Exit Self Refresh to Active Delay */ 134 135/* Memory Device Register -> SDRAM */ 136#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 137#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 138#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 139#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 140#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 141#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 142#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 143#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 144#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 145#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 146#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 147#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 148#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 149#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 150#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 151#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 152#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 153#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 154 155/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 156#define CONFIG_SYS_SMC0_SETUP0_VAL \ 157 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 158 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 159#define CONFIG_SYS_SMC0_PULSE0_VAL \ 160 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 161 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 162#define CONFIG_SYS_SMC0_CYCLE0_VAL \ 163 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 164#define CONFIG_SYS_SMC0_MODE0_VAL \ 165 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 166 AT91_SMC_MODE_DBW_16 | \ 167 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 168 169/* user reset enable */ 170#define CONFIG_SYS_RSTC_RMR_VAL \ 171 (AT91_RSTC_KEY | \ 172 AT91_RSTC_MR_URSTEN | \ 173 AT91_RSTC_MR_ERSTL(15)) 174 175/* Disable Watchdog */ 176#define CONFIG_SYS_WDTC_WDMR_VAL \ 177 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 178 AT91_WDT_MR_WDV(0xfff) | \ 179 AT91_WDT_MR_WDDIS | \ 180 AT91_WDT_MR_WDD(0xfff)) 181 182#endif 183#include <linux/stringify.h> 184#endif 185 186/* NAND flash */ 187#ifdef CONFIG_CMD_NAND 188#define CONFIG_SYS_MAX_NAND_DEVICE 1 189#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 190#define CONFIG_SYS_NAND_DBW_8 1 191/* our ALE is AD21 */ 192#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 193/* our CLE is AD22 */ 194#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 195#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 196#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 197#endif 198 199/* Ethernet */ 200#define CONFIG_RESET_PHY_R 1 201#define CONFIG_AT91_WANTS_COMMON_PHY 202 203/* USB */ 204#define CONFIG_USB_ATMEL 205#define CONFIG_USB_ATMEL_CLK_SEL_PLLB 206#define CONFIG_USB_OHCI_NEW 1 207#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 208#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 209#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 210#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 211 212#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 213 214#ifdef CONFIG_SYS_USE_DATAFLASH 215 216/* bootstrap + u-boot + env + linux in dataflash on CS0 */ 217#define CONFIG_BOOTCOMMAND "sf probe 0; " \ 218 "sf read 0x22000000 0x84000 0x294000; " \ 219 "bootm 0x22000000" 220 221#elif CONFIG_SYS_USE_NANDFLASH 222 223/* bootstrap + u-boot + env + linux in nandflash */ 224#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 225#endif 226 227/* 228 * Size of malloc() pool 229 */ 230#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 231 232#endif 233