LXR uboot/include/configs/imx8mm

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2021 Gateworks Corporation
   4 */
   5
   6#ifndef __IMX8MM_VENICE_H
   7#define __IMX8MM_VENICE_H
   8
   9#include <asm/arch/imx-regs.h>
  10#include <linux/sizes.h>
  11
  12#define CONFIG_SPL_MAX_SIZE             (148 * 1024)
  13#define CONFIG_SYS_MONITOR_LEN          SZ_512K
  14#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  15#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  16#define CONFIG_SYS_UBOOT_BASE   \
  17        (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  18
  19#ifdef CONFIG_SPL_BUILD
  20#define CONFIG_SPL_STACK                0x920000
  21#define CONFIG_SPL_BSS_START_ADDR       0x910000
  22#define CONFIG_SPL_BSS_MAX_SIZE         SZ_8K   /* 8 KB */
  23#define CONFIG_SYS_SPL_MALLOC_START     0x42200000
  24#define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_512K /* 512 KB */
  25
  26/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  27#define CONFIG_MALLOC_F_ADDR            0x930000
  28/* For RAW image gives a error info not panic */
  29#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  30
  31#endif
  32
  33#define MEM_LAYOUT_ENV_SETTINGS \
  34        "fdt_addr_r=0x44000000\0" \
  35        "kernel_addr_r=0x42000000\0" \
  36        "ramdisk_addr_r=0x46400000\0" \
  37        "scriptaddr=0x46000000\0"
  38
  39/* Link Definitions */
  40#define CONFIG_LOADADDR                 0x40480000
  41#define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
  42
  43/* Enable Distro Boot */
  44#ifndef CONFIG_SPL_BUILD
  45#define BOOT_TARGET_DEVICES(func) \
  46        func(MMC, mmc, 1) \
  47        func(MMC, mmc, 2) \
  48        func(DHCP, dhcp, na)
  49#include <config_distro_bootcmd.h>
  50#undef CONFIG_ISO_PARTITION
  51#else
  52#define BOOTENV
  53#endif
  54
  55/* Initial environment variables */
  56#define CONFIG_EXTRA_ENV_SETTINGS \
  57        BOOTENV \
  58        MEM_LAYOUT_ENV_SETTINGS \
  59        "script=boot.scr\0" \
  60        "bootm_size=0x10000000\0" \
  61        "ipaddr=192.168.1.22\0" \
  62        "serverip=192.168.1.146\0" \
  63        "dev=2\0" \
  64        "preboot=gsc wd-disable\0" \
  65        "console=ttymxc1,115200\0" \
  66        "update_firmware=" \
  67                "tftpboot $loadaddr $image && " \
  68                "setexpr blkcnt $filesize + 0x1ff && " \
  69                "setexpr blkcnt $blkcnt / 0x200 && " \
  70                "mmc dev $dev && " \
  71                "mmc write $loadaddr 0x42 $blkcnt\0" \
  72        "boot_net=" \
  73                "tftpboot $kernel_addr_r $image && " \
  74                "booti $kernel_addr_r - $fdtcontroladdr\0" \
  75        "update_rootfs=" \
  76                "tftpboot $loadaddr $image && " \
  77                "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
  78        "update_all=" \
  79                "tftpboot $loadaddr $image && " \
  80                "gzwrite mmc $dev $loadaddr $filesize\0" \
  81        "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
  82
  83#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  84#define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
  85#define CONFIG_SYS_INIT_SP_OFFSET \
  86        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  87#define CONFIG_SYS_INIT_SP_ADDR \
  88        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  89
  90/* Size of malloc() pool */
  91#define CONFIG_SYS_MALLOC_LEN           SZ_32M
  92#define CONFIG_SYS_SDRAM_BASE           0x40000000
  93
  94/* SDRAM configuration */
  95#define PHYS_SDRAM                      0x40000000
  96#define PHYS_SDRAM_SIZE                 SZ_1G /* 1GB DDR */
  97#define CONFIG_SYS_BOOTM_LEN            SZ_256M
  98
  99/* UART */
 100#define CONFIG_MXC_UART_BASE            UART2_BASE_ADDR
 101
 102/* Monitor Command Prompt */
 103#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 104#define CONFIG_SYS_CBSIZE               SZ_2K
 105#define CONFIG_SYS_MAXARGS              64
 106#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 107#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 108                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 109
 110/* USDHC */
 111#define CONFIG_SYS_FSL_USDHC_NUM        2
 112#define CONFIG_SYS_FSL_ESDHC_ADDR       0
 113#define CONFIG_SYS_MMC_IMG_LOAD_PART    1
 114
 115/* I2C */
 116#define CONFIG_SYS_I2C_SPEED            100000
 117
 118/* FEC */
 119#define CONFIG_ETHPRIME                 "eth0"
 120#define CONFIG_FEC_XCV_TYPE             RGMII
 121#define CONFIG_FEC_MXC_PHYADDR          0
 122#define FEC_QUIRK_ENET_MAC
 123#define IMX_FEC_BASE                    0x30BE0000
 124
 125#endif
 126