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6
7#ifndef __LS2_RDB_H
8#define __LS2_RDB_H
9
10#include "ls2080a_common.h"
11
12#ifdef CONFIG_FSL_QSPI
13#ifdef CONFIG_TARGET_LS2081ARDB
14#define CONFIG_QIXIS_I2C_ACCESS
15#endif
16#if !CONFIG_IS_ENABLED(DM_I2C)
17#define CONFIG_SYS_I2C_EARLY_INIT
18#endif
19#endif
20
21#define I2C_MUX_CH_VOL_MONITOR 0xa
22#define I2C_VOL_MONITOR_ADDR 0x38
23#define CONFIG_VOL_MONITOR_IR36021_READ
24#define CONFIG_VOL_MONITOR_IR36021_SET
25
26#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
27#ifndef CONFIG_SPL_BUILD
28#define CONFIG_VID
29#endif
30
31#define IR_VDD_STEP_DOWN 5
32#define IR_VDD_STEP_UP 5
33
34#define VDD_MV_MIN 819
35#define VDD_MV_MAX 1212
36
37#ifndef __ASSEMBLY__
38unsigned long get_board_sys_clk(void);
39#endif
40
41#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
42#define CONFIG_DDR_CLK_FREQ 133333333
43#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
44
45#define CONFIG_DDR_SPD
46#define CONFIG_DDR_ECC
47#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49#define SPD_EEPROM_ADDRESS1 0x51
50#define SPD_EEPROM_ADDRESS2 0x52
51#define SPD_EEPROM_ADDRESS3 0x53
52#define SPD_EEPROM_ADDRESS4 0x54
53#define SPD_EEPROM_ADDRESS5 0x55
54#define SPD_EEPROM_ADDRESS6 0x56
55#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
56#define CONFIG_SYS_SPD_BUS_NUM 0
57#define CONFIG_DIMM_SLOTS_PER_CTLR 2
58#define CONFIG_CHIP_SELECTS_PER_CTRL 4
59#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
60#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
61#endif
62
63
64#define CONFIG_SCSI_AHCI_PLAT
65
66#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
67#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
68
69#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
70#define CONFIG_SYS_SCSI_MAX_LUN 1
71#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
72 CONFIG_SYS_SCSI_MAX_LUN)
73
74#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
75
76#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
77#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
78#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
79
80#define CONFIG_SYS_NOR0_CSPR \
81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
82 CSPR_PORT_SIZE_16 | \
83 CSPR_MSEL_NOR | \
84 CSPR_V)
85#define CONFIG_SYS_NOR0_CSPR_EARLY \
86 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
87 CSPR_PORT_SIZE_16 | \
88 CSPR_MSEL_NOR | \
89 CSPR_V)
90#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
91#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
92 FTIM0_NOR_TEADC(0x5) | \
93 FTIM0_NOR_TEAHC(0x5))
94#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
95 FTIM1_NOR_TRAD_NOR(0x1a) |\
96 FTIM1_NOR_TSEQRAD_NOR(0x13))
97#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
98 FTIM2_NOR_TCH(0x4) | \
99 FTIM2_NOR_TWPH(0x0E) | \
100 FTIM2_NOR_TWP(0x1c))
101#define CONFIG_SYS_NOR_FTIM3 0x04000000
102#define CONFIG_SYS_IFC_CCR 0x01000000
103
104#ifdef CONFIG_MTD_NOR_FLASH
105#define CONFIG_SYS_FLASH_QUIET_TEST
106#define CONFIG_FLASH_SHOW_PROGRESS 45
107
108#define CONFIG_SYS_MAX_FLASH_BANKS 1
109#define CONFIG_SYS_MAX_FLASH_SECT 1024
110#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
111#define CONFIG_SYS_FLASH_WRITE_TOUT 500
112
113#define CONFIG_SYS_FLASH_EMPTY_INFO
114#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
115 CONFIG_SYS_FLASH_BASE + 0x40000000}
116#endif
117
118#define CONFIG_NAND_FSL_IFC
119#define CONFIG_SYS_NAND_MAX_ECCPOS 256
120#define CONFIG_SYS_NAND_MAX_OOBFREE 2
121
122#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
123#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
124 | CSPR_PORT_SIZE_8 \
125 | CSPR_MSEL_NAND \
126 | CSPR_V)
127#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
128
129#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
130 | CSOR_NAND_ECC_DEC_EN \
131 | CSOR_NAND_ECC_MODE_4 \
132 | CSOR_NAND_RAL_3 \
133 | CSOR_NAND_PGS_4K \
134 | CSOR_NAND_SPRZ_224 \
135 | CSOR_NAND_PB(128))
136
137#define CONFIG_SYS_NAND_ONFI_DETECTION
138
139
140#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
141 FTIM0_NAND_TWP(0x30) | \
142 FTIM0_NAND_TWCHT(0x0e) | \
143 FTIM0_NAND_TWH(0x14))
144#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
145 FTIM1_NAND_TWBE(0xab) | \
146 FTIM1_NAND_TRR(0x1c) | \
147 FTIM1_NAND_TRP(0x30))
148#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
149 FTIM2_NAND_TREH(0x14) | \
150 FTIM2_NAND_TWHRE(0x3c))
151#define CONFIG_SYS_NAND_FTIM3 0x0
152
153#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
154#define CONFIG_SYS_MAX_NAND_DEVICE 1
155#define CONFIG_MTD_NAND_VERIFY_WRITE
156
157#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
158#define CONFIG_FSL_QIXIS
159#define QIXIS_LBMAP_SWITCH 0x06
160#define QIXIS_LBMAP_MASK 0x0f
161#define QIXIS_LBMAP_SHIFT 0
162#define QIXIS_LBMAP_DFLTBANK 0x00
163#define QIXIS_LBMAP_ALTBANK 0x04
164#define QIXIS_LBMAP_NAND 0x09
165#define QIXIS_RST_CTL_RESET 0x31
166#define QIXIS_RST_CTL_RESET_EN 0x30
167#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
168#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
169#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
170#define QIXIS_RCW_SRC_NAND 0x119
171#define QIXIS_RST_FORCE_MEM 0x01
172
173#define CONFIG_SYS_CSPR3_EXT (0x0)
174#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
175 | CSPR_PORT_SIZE_8 \
176 | CSPR_MSEL_GPCM \
177 | CSPR_V)
178#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
179 | CSPR_PORT_SIZE_8 \
180 | CSPR_MSEL_GPCM \
181 | CSPR_V)
182
183#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
184#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
185
186#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
187 FTIM0_GPCM_TEADC(0x0e) | \
188 FTIM0_GPCM_TEAHC(0x0e))
189#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
190 FTIM1_GPCM_TRAD(0x3f))
191#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
192 FTIM2_GPCM_TCH(0xf) | \
193 FTIM2_GPCM_TWP(0x3E))
194#define CONFIG_SYS_CS3_FTIM3 0x0
195
196#if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
197#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
198#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
199#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
200#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
201#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
202#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
203#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
204#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
205#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
206#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
207#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
208#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
209#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
210#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
211#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
212#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
213#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
214
215#define CONFIG_SPL_PAD_TO 0x80000
216#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
217#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
218#else
219#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
220#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
221#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
222#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
223#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
224#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
225#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
226#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
227#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
228#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
229#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
230#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
231#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
232#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
233#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
234#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
235#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
236#endif
237
238
239#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
240#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
241#endif
242#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
243
244#ifdef CONFIG_TARGET_LS2081ARDB
245#define CONFIG_FSL_QIXIS
246#define QIXIS_QMAP_MASK 0x07
247#define QIXIS_QMAP_SHIFT 5
248#define QIXIS_LBMAP_DFLTBANK 0x00
249#define QIXIS_LBMAP_QSPI 0x00
250#define QIXIS_RCW_SRC_QSPI 0x62
251#define QIXIS_LBMAP_ALTBANK 0x20
252#define QIXIS_RST_CTL_RESET 0x31
253#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
254#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
255#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
256#define QIXIS_LBMAP_MASK 0x0f
257#define QIXIS_RST_CTL_RESET_EN 0x30
258#endif
259
260
261
262
263#ifdef CONFIG_TARGET_LS2081ARDB
264#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
265#endif
266#define I2C_MUX_PCA_ADDR 0x75
267#define I2C_MUX_PCA_ADDR_PRI 0x75
268
269
270#define I2C_MUX_CH_DEFAULT 0x8
271
272
273#if defined(CONFIG_FSL_DSPI)
274#define CONFIG_SPI_FLASH_STMICRO
275#endif
276
277
278
279
280#define RTC
281#ifdef CONFIG_TARGET_LS2081ARDB
282#define CONFIG_SYS_I2C_RTC_ADDR 0x51
283#else
284#define CONFIG_RTC_DS3231 1
285#define CONFIG_SYS_I2C_RTC_ADDR 0x68
286#endif
287
288
289#define CONFIG_ID_EEPROM
290#define CONFIG_SYS_I2C_EEPROM_NXID
291#define CONFIG_SYS_EEPROM_BUS_NUM 0
292#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
293#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
294#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
295#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
296
297#define CONFIG_FSL_MEMAC
298
299#ifdef CONFIG_PCI
300#define CONFIG_PCI_SCAN_SHOW
301#endif
302
303
304#ifdef CONFIG_MMC
305#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
306#endif
307
308#define BOOT_TARGET_DEVICES(func) \
309 func(USB, usb, 0) \
310 func(MMC, mmc, 0) \
311 func(SCSI, scsi, 0) \
312 func(DHCP, dhcp, na)
313#include <config_distro_bootcmd.h>
314
315#ifdef CONFIG_TFABOOT
316#define QSPI_MC_INIT_CMD \
317 "sf probe 0:0; " \
318 "sf read 0x80640000 0x640000 0x80000; " \
319 "env exists secureboot && " \
320 "esbc_validate 0x80640000 && " \
321 "esbc_validate 0x80680000; " \
322 "sf read 0x80a00000 0xa00000 0x300000; " \
323 "sf read 0x80e00000 0xe00000 0x100000; " \
324 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
325#define SD_MC_INIT_CMD \
326 "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
327 "mmc read 0x80e00000 0x7000 0x800;" \
328 "env exists secureboot && " \
329 "mmc read 0x80640000 0x3200 0x20 && " \
330 "mmc read 0x80680000 0x3400 0x20 && " \
331 "esbc_validate 0x80640000 && " \
332 "esbc_validate 0x80680000 ;" \
333 "fsl_mc start mc 0x80a00000 0x80e00000\0"
334#define IFC_MC_INIT_CMD \
335 "env exists secureboot && " \
336 "esbc_validate 0x580640000 && " \
337 "esbc_validate 0x580680000; " \
338 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
339#else
340#ifdef CONFIG_QSPI_BOOT
341#define MC_INIT_CMD \
342 "mcinitcmd=sf probe 0:0; " \
343 "sf read 0x80640000 0x640000 0x80000; " \
344 "env exists secureboot && " \
345 "esbc_validate 0x80640000 && " \
346 "esbc_validate 0x80680000; " \
347 "sf read 0x80a00000 0xa00000 0x300000; " \
348 "sf read 0x80e00000 0xe00000 0x100000; " \
349 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
350#elif defined(CONFIG_SD_BOOT)
351#define MC_INIT_CMD \
352 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
353 "mmc read 0x80100000 0x7000 0x800;" \
354 "env exists secureboot && " \
355 "mmc read 0x80640000 0x3200 0x20 && " \
356 "mmc read 0x80680000 0x3400 0x20 && " \
357 "esbc_validate 0x80640000 && " \
358 "esbc_validate 0x80680000 ;" \
359 "fsl_mc start mc 0x80000000 0x80100000\0" \
360 "mcmemsize=0x70000000\0"
361#else
362#define MC_INIT_CMD \
363 "mcinitcmd=env exists secureboot && " \
364 "esbc_validate 0x580640000 && " \
365 "esbc_validate 0x580680000; " \
366 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
367#endif
368#endif
369
370
371#undef CONFIG_EXTRA_ENV_SETTINGS
372#ifdef CONFIG_TFABOOT
373#define CONFIG_EXTRA_ENV_SETTINGS \
374 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
375 "ramdisk_addr=0x800000\0" \
376 "ramdisk_size=0x2000000\0" \
377 "fdt_high=0xa0000000\0" \
378 "initrd_high=0xffffffffffffffff\0" \
379 "fdt_addr=0x64f00000\0" \
380 "kernel_addr=0x581000000\0" \
381 "kernel_start=0x1000000\0" \
382 "kernelheader_start=0x800000\0" \
383 "scriptaddr=0x80000000\0" \
384 "scripthdraddr=0x80080000\0" \
385 "fdtheader_addr_r=0x80100000\0" \
386 "kernelheader_addr_r=0x80200000\0" \
387 "kernelheader_addr=0x580600000\0" \
388 "kernel_addr_r=0x81000000\0" \
389 "kernelheader_size=0x40000\0" \
390 "fdt_addr_r=0x90000000\0" \
391 "load_addr=0xa0000000\0" \
392 "kernel_size=0x2800000\0" \
393 "kernel_addr_sd=0x8000\0" \
394 "kernel_size_sd=0x14000\0" \
395 "console=ttyAMA0,38400n8\0" \
396 "mcmemsize=0x70000000\0" \
397 "sd_bootcmd=echo Trying load from SD ..;" \
398 "mmcinfo; mmc read $load_addr " \
399 "$kernel_addr_sd $kernel_size_sd && " \
400 "bootm $load_addr#$board\0" \
401 QSPI_MC_INIT_CMD \
402 BOOTENV \
403 "boot_scripts=ls2088ardb_boot.scr\0" \
404 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
405 "scan_dev_for_boot_part=" \
406 "part list ${devtype} ${devnum} devplist; " \
407 "env exists devplist || setenv devplist 1; " \
408 "for distro_bootpart in ${devplist}; do " \
409 "if fstype ${devtype} " \
410 "${devnum}:${distro_bootpart} " \
411 "bootfstype; then " \
412 "run scan_dev_for_boot; " \
413 "fi; " \
414 "done\0" \
415 "boot_a_script=" \
416 "load ${devtype} ${devnum}:${distro_bootpart} " \
417 "${scriptaddr} ${prefix}${script}; " \
418 "env exists secureboot && load ${devtype} " \
419 "${devnum}:${distro_bootpart} " \
420 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
421 "&& esbc_validate ${scripthdraddr};" \
422 "source ${scriptaddr}\0" \
423 "qspi_bootcmd=echo Trying load from qspi..;" \
424 "sf probe && sf read $load_addr " \
425 "$kernel_start $kernel_size ; env exists secureboot &&" \
426 "sf read $kernelheader_addr_r $kernelheader_start " \
427 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
428 " bootm $load_addr#$board\0" \
429 "nor_bootcmd=echo Trying load from nor..;" \
430 "cp.b $kernel_addr $load_addr " \
431 "$kernel_size ; env exists secureboot && " \
432 "cp.b $kernelheader_addr $kernelheader_addr_r " \
433 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
434 "bootm $load_addr#$board\0"
435#else
436#define CONFIG_EXTRA_ENV_SETTINGS \
437 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
438 "ramdisk_addr=0x800000\0" \
439 "ramdisk_size=0x2000000\0" \
440 "fdt_high=0xa0000000\0" \
441 "initrd_high=0xffffffffffffffff\0" \
442 "fdt_addr=0x64f00000\0" \
443 "kernel_addr=0x581000000\0" \
444 "kernel_start=0x1000000\0" \
445 "kernelheader_start=0x600000\0" \
446 "scriptaddr=0x80000000\0" \
447 "scripthdraddr=0x80080000\0" \
448 "fdtheader_addr_r=0x80100000\0" \
449 "kernelheader_addr_r=0x80200000\0" \
450 "kernelheader_addr=0x580600000\0" \
451 "kernel_addr_r=0x81000000\0" \
452 "kernelheader_size=0x40000\0" \
453 "fdt_addr_r=0x90000000\0" \
454 "load_addr=0xa0000000\0" \
455 "kernel_size=0x2800000\0" \
456 "kernel_addr_sd=0x8000\0" \
457 "kernel_size_sd=0x14000\0" \
458 "console=ttyAMA0,38400n8\0" \
459 "mcmemsize=0x70000000\0" \
460 "sd_bootcmd=echo Trying load from SD ..;" \
461 "mmcinfo; mmc read $load_addr " \
462 "$kernel_addr_sd $kernel_size_sd && " \
463 "bootm $load_addr#$board\0" \
464 MC_INIT_CMD \
465 BOOTENV \
466 "boot_scripts=ls2088ardb_boot.scr\0" \
467 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
468 "scan_dev_for_boot_part=" \
469 "part list ${devtype} ${devnum} devplist; " \
470 "env exists devplist || setenv devplist 1; " \
471 "for distro_bootpart in ${devplist}; do " \
472 "if fstype ${devtype} " \
473 "${devnum}:${distro_bootpart} " \
474 "bootfstype; then " \
475 "run scan_dev_for_boot; " \
476 "fi; " \
477 "done\0" \
478 "boot_a_script=" \
479 "load ${devtype} ${devnum}:${distro_bootpart} " \
480 "${scriptaddr} ${prefix}${script}; " \
481 "env exists secureboot && load ${devtype} " \
482 "${devnum}:${distro_bootpart} " \
483 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
484 "env exists secureboot " \
485 "&& esbc_validate ${scripthdraddr};" \
486 "source ${scriptaddr}\0" \
487 "qspi_bootcmd=echo Trying load from qspi..;" \
488 "sf probe && sf read $load_addr " \
489 "$kernel_start $kernel_size ; env exists secureboot &&" \
490 "sf read $kernelheader_addr_r $kernelheader_start " \
491 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
492 " bootm $load_addr#$board\0" \
493 "nor_bootcmd=echo Trying load from nor..;" \
494 "cp.b $kernel_addr $load_addr " \
495 "$kernel_size ; env exists secureboot && " \
496 "cp.b $kernelheader_addr $kernelheader_addr_r " \
497 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
498 "bootm $load_addr#$board\0"
499#endif
500
501#ifdef CONFIG_TFABOOT
502#define QSPI_NOR_BOOTCOMMAND \
503 "sf probe 0:0; " \
504 "sf read 0x806c0000 0x6c0000 0x40000; " \
505 "env exists mcinitcmd && env exists secureboot "\
506 "&& esbc_validate 0x806c0000; " \
507 "sf read 0x80d00000 0xd00000 0x100000; " \
508 "env exists mcinitcmd && " \
509 "fsl_mc lazyapply dpl 0x80d00000; " \
510 "run distro_bootcmd;run qspi_bootcmd; " \
511 "env exists secureboot && esbc_halt;"
512
513
514#define SD_BOOTCOMMAND \
515 "env exists mcinitcmd && env exists secureboot "\
516 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
517 "&& esbc_validate $load_addr; " \
518 "env exists mcinitcmd && run mcinitcmd " \
519 "&& mmc read 0x80d00000 0x6800 0x800 " \
520 "&& fsl_mc lazyapply dpl 0x80d00000; " \
521 "run distro_bootcmd;run sd_bootcmd; " \
522 "env exists secureboot && esbc_halt;"
523
524
525#define IFC_NOR_BOOTCOMMAND \
526 "env exists mcinitcmd && env exists secureboot "\
527 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
528 "&& fsl_mc lazyapply dpl 0x580d00000;" \
529 "run distro_bootcmd;run nor_bootcmd; " \
530 "env exists secureboot && esbc_halt;"
531#else
532#undef CONFIG_BOOTCOMMAND
533#ifdef CONFIG_QSPI_BOOT
534
535#define CONFIG_BOOTCOMMAND \
536 "sf probe 0:0; " \
537 "sf read 0x806c0000 0x6c0000 0x40000; " \
538 "env exists mcinitcmd && env exists secureboot "\
539 "&& esbc_validate 0x806C0000; " \
540 "sf read 0x80d00000 0xd00000 0x100000; " \
541 "env exists mcinitcmd && " \
542 "fsl_mc lazyapply dpl 0x80d00000; " \
543 "run distro_bootcmd;run qspi_bootcmd; " \
544 "env exists secureboot && esbc_halt;"
545#elif defined(CONFIG_SD_BOOT)
546
547#define CONFIG_BOOTCOMMAND \
548 "env exists mcinitcmd && env exists secureboot "\
549 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
550 "&& esbc_validate $load_addr; " \
551 "env exists mcinitcmd && run mcinitcmd " \
552 "&& mmc read 0x88000000 0x6800 0x800 " \
553 "&& fsl_mc lazyapply dpl 0x88000000; " \
554 "run distro_bootcmd;run sd_bootcmd; " \
555 "env exists secureboot && esbc_halt;"
556#else
557
558#define CONFIG_BOOTCOMMAND \
559 "env exists mcinitcmd && env exists secureboot "\
560 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
561 "&& fsl_mc lazyapply dpl 0x580d00000;" \
562 "run distro_bootcmd;run nor_bootcmd; " \
563 "env exists secureboot && esbc_halt;"
564#endif
565#endif
566
567
568#ifdef CONFIG_FSL_MC_ENET
569#ifdef CONFIG_QSPI_BOOT
570#define CONFIG_CORTINA_FW_ADDR 0x20980000
571#else
572#define CONFIG_CORTINA_FW_ADDR 0x580980000
573#endif
574#define CONFIG_CORTINA_FW_LENGTH 0x40000
575
576#define CORTINA_PHY_ADDR1 0x10
577#define CORTINA_PHY_ADDR2 0x11
578#define CORTINA_PHY_ADDR3 0x12
579#define CORTINA_PHY_ADDR4 0x13
580#define AQ_PHY_ADDR1 0x00
581#define AQ_PHY_ADDR2 0x01
582#define AQ_PHY_ADDR3 0x02
583#define AQ_PHY_ADDR4 0x03
584#define AQR405_IRQ_MASK 0x36
585
586#define CONFIG_ETHPRIME "DPMAC1@xgmii"
587#endif
588
589#include <asm/fsl_secure_boot.h>
590
591#endif
592
