LXR uboot/include/configs/mpc8308

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   5 *
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11#include <linux/stringify.h>
  12
  13/*
  14 * High Level Configuration Options
  15 */
  16#define CONFIG_E300             1 /* E300 family */
  17
  18/*
  19 * On-board devices
  20 *
  21 * TSECs
  22 */
  23#define CONFIG_TSEC1
  24#define CONFIG_TSEC2
  25
  26#define CONFIG_SYS_GPIO1_PRELIM
  27/* GPIO Default input/output settings */
  28#define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
  29/*
  30 * Default GPIO values:
  31 * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
  32 */
  33#define CONFIG_SYS_GPIO1_DAT        0x08008C00
  34
  35/*
  36 * SERDES
  37 */
  38#define CONFIG_FSL_SERDES
  39#define CONFIG_FSL_SERDES1      0xe3000
  40
  41/*
  42 * DDR Setup
  43 */
  44#define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  45#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  46#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  47                                | DDRCDR_PZ_LOZ \
  48                                | DDRCDR_NZ_LOZ \
  49                                | DDRCDR_ODT \
  50                                | DDRCDR_Q_DRN)
  51                                /* 0x7b880001 */
  52/*
  53 * Manually set up DDR parameters
  54 * consist of two chips HY5PS12621BFP-C4 from HYNIX
  55 */
  56
  57#define CONFIG_SYS_DDR_SIZE             128 /* MB */
  58
  59#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  60#define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  61                                        | CSCONFIG_ODT_RD_NEVER \
  62                                        | CSCONFIG_ODT_WR_ONLY_CURRENT \
  63                                        | CSCONFIG_ROW_BIT_13 \
  64                                        | CSCONFIG_COL_BIT_10)
  65                                        /* 0x80010102 */
  66#define CONFIG_SYS_DDR_TIMING_3 0x00000000
  67#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  68                                | (0 << TIMING_CFG0_WRT_SHIFT) \
  69                                | (0 << TIMING_CFG0_RRT_SHIFT) \
  70                                | (0 << TIMING_CFG0_WWT_SHIFT) \
  71                                | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  72                                | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  73                                | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  74                                | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  75                                /* 0x00220802 */
  76#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  77                                | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  78                                | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  79                                | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  80                                | (6 << TIMING_CFG1_REFREC_SHIFT) \
  81                                | (2 << TIMING_CFG1_WRREC_SHIFT) \
  82                                | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  83                                | (2 << TIMING_CFG1_WRTORD_SHIFT))
  84                                /* 0x27256222 */
  85#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  86                                | (4 << TIMING_CFG2_CPO_SHIFT) \
  87                                | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  88                                | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  89                                | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  90                                | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  91                                | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  92                                /* 0x121048c5 */
  93#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
  94                                | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  95                                /* 0x03600100 */
  96#define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  97                                | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  98                                | SDRAM_CFG_DBW_32)
  99                                /* 0x43080000 */
 100
 101#define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 102#define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 103                                | (0x0232 << SDRAM_MODE_SD_SHIFT))
 104                                /* ODT 150ohm CL=3, AL=1 on SDRAM */
 105#define CONFIG_SYS_DDR_MODE2            0x00000000
 106
 107/*
 108 * Memory test
 109 */
 110
 111/*
 112 * The reserved memory
 113 */
 114#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 115
 116#define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 117#define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 118
 119/*
 120 * Initial RAM Base Address Setup
 121 */
 122#define CONFIG_SYS_INIT_RAM_LOCK        1
 123#define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 124#define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 125#define CONFIG_SYS_GBL_DATA_OFFSET      \
 126        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 127
 128/*
 129 * FLASH on the Local Bus
 130 */
 131#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 132
 133#define CONFIG_SYS_FLASH_BASE           0xFC000000 /* FLASH base address */
 134#define CONFIG_SYS_FLASH_SIZE           64 /* FLASH size is 64M */
 135
 136
 137#define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 138#define CONFIG_SYS_MAX_FLASH_SECT       512
 139
 140/* Flash Erase Timeout (ms) */
 141#define CONFIG_SYS_FLASH_ERASE_TOUT     (1000 * 1024)
 142/* Flash Write Timeout (ms) */
 143#define CONFIG_SYS_FLASH_WRITE_TOUT     (500 * 1024)
 144
 145/*
 146 * SJA1000 CAN controller on Local Bus
 147 */
 148#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
 149
 150
 151/*
 152 * CPLD on Local Bus
 153 */
 154#define CONFIG_SYS_CPLD_BASE    0xFBFF8000
 155
 156
 157/*
 158 * Serial Port
 159 */
 160#undef CONFIG_SERIAL_SOFTWARE_FIFO
 161#define CONFIG_SYS_NS16550_SERIAL
 162#define CONFIG_SYS_NS16550_REG_SIZE     1
 163#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 164
 165#define CONFIG_SYS_BAUDRATE_TABLE  \
 166        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 167
 168#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 169#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 170
 171/* I2C */
 172#define CONFIG_SYS_I2C
 173#define CONFIG_SYS_I2C_FSL
 174#define CONFIG_SYS_FSL_I2C_SPEED        400000
 175#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 176#define CONFIG_SYS_FSL_I2C2_SPEED       400000
 177#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 178#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 179#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 180
 181/*
 182 * General PCI
 183 * Addresses are mapped 1-1.
 184 */
 185#define CONFIG_SYS_PCIE1_BASE           0xA0000000
 186#define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 187#define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 188#define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 189#define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 190#define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 191#define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 192#define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 193#define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 194
 195/* enable PCIE clock */
 196#define CONFIG_SYS_SCCR_PCIEXP1CM       1
 197
 198#define CONFIG_PCI_INDIRECT_BRIDGE
 199#define CONFIG_PCIE
 200
 201#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 202#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 203
 204/*
 205 * TSEC
 206 */
 207#define CONFIG_SYS_TSEC1_OFFSET 0x24000
 208#define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 209#define CONFIG_SYS_TSEC2_OFFSET 0x25000
 210#define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 211
 212/*
 213 * TSEC ethernet configuration
 214 */
 215#define CONFIG_TSEC1_NAME       "eTSEC0"
 216#define CONFIG_TSEC2_NAME       "eTSEC1"
 217#define TSEC1_PHY_ADDR          1
 218#define TSEC2_PHY_ADDR          2
 219#define TSEC1_PHYIDX            0
 220#define TSEC2_PHYIDX            0
 221#define TSEC1_FLAGS             0
 222#define TSEC2_FLAGS             0
 223
 224/* Options are: eTSEC[0-1] */
 225#define CONFIG_ETHPRIME         "eTSEC0"
 226
 227/*
 228 * Environment
 229 */
 230
 231#define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 232#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 233
 234/*
 235 * BOOTP options
 236 */
 237#define CONFIG_BOOTP_BOOTFILESIZE
 238
 239/*
 240 * Miscellaneous configurable options
 241 */
 242#define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 243
 244#define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 245
 246/* Boot Argument Buffer Size */
 247#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 248
 249/*
 250 * For booting Linux, the board info and command line data
 251 * have to be in the first 8 MB of memory, since this is
 252 * the maximum mapped by the Linux kernel during initialization.
 253 */
 254#define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 255
 256/*
 257 * Environment Configuration
 258 */
 259
 260#if defined(CONFIG_TSEC_ENET)
 261#define CONFIG_HAS_ETH0
 262#define CONFIG_HAS_ETH1
 263#endif
 264
 265#define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 266
 267
 268#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 269        "netdev=eth0\0"                                                 \
 270        "consoledev=ttyS0\0"                                            \
 271        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 272                "nfsroot=${serverip}:${rootpath}\0"                     \
 273        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 274        "addip=setenv bootargs ${bootargs} "                            \
 275                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 276                ":${hostname}:${netdev}:off panic=1\0"                  \
 277        "addtty=setenv bootargs ${bootargs}"                            \
 278                " console=${consoledev},${baudrate}\0"                  \
 279        "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 280        "addmisc=setenv bootargs ${bootargs}\0"                         \
 281        "kernel_addr=FC0A0000\0"                                        \
 282        "fdt_addr=FC2A0000\0"                                           \
 283        "ramdisk_addr=FC2C0000\0"                                       \
 284        "u-boot=mpc8308_p1m/u-boot.bin\0"                               \
 285        "kernel_addr_r=1000000\0"                                       \
 286        "fdt_addr_r=C00000\0"                                           \
 287        "hostname=mpc8308_p1m\0"                                        \
 288        "bootfile=mpc8308_p1m/uImage\0"                                 \
 289        "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"                         \
 290        "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 291        "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 292                "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 293        "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 294                "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 295        "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 296                "tftp ${fdt_addr_r} ${fdtfile};"                        \
 297                "run nfsargs addip addtty addmtd addmisc;"              \
 298                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 299        "bootcmd=run flash_self\0"                                      \
 300        "load=tftp ${loadaddr} ${u-boot}\0"                             \
 301        "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 302                " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 303                " +${filesize};cp.b ${fileaddr} "                       \
 304                __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 305        "upd=run load update\0"                                         \
 306
 307#endif  /* __CONFIG_H */
 308