uboot/include/configs/tegra186-common.h
<<
>>
Prefs
   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright 2013-2016, NVIDIA CORPORATION.
   4 */
   5
   6#ifndef _TEGRA186_COMMON_H_
   7#define _TEGRA186_COMMON_H_
   8
   9#include "tegra-common.h"
  10
  11/*
  12 * NS16550 Configuration
  13 */
  14#define V_NS16550_CLK           408000000       /* 408MHz (pllp_out0) */
  15
  16/*-----------------------------------------------------------------------
  17 * Physical Memory Map
  18 */
  19
  20/* Generic Interrupt Controller */
  21#define CONFIG_GICV2
  22
  23#undef FDTFILE
  24#define BOOTENV_EFI_SET_FDTFILE_FALLBACK                                  \
  25        "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then "               \
  26          "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; "           \
  27        "fi; "
  28
  29/*
  30 * Memory layout for where various images get loaded by boot scripts:
  31 *
  32 * scriptaddr can be pretty much anywhere that doesn't conflict with something
  33 *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  34 *
  35 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  36 *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
  37 *
  38 * kernel_addr_r must be within the first 128M of RAM in order for the
  39 *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  40 *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  41 *   should not overlap that area, or the kernel will have to copy itself
  42 *   somewhere else before decompression. Similarly, the address of any other
  43 *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
  44 *   this up to 16M allows for a sizable kernel to be decompressed below the
  45 *   compressed load address.
  46 *
  47 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  48 *   the compressed kernel to be up to 16M too.
  49 *
  50 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  51 *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  52 */
  53#define CONFIG_LOADADDR 0x80080000
  54#define MEM_LAYOUT_ENV_SETTINGS \
  55        "scriptaddr=0x90000000\0" \
  56        "pxefile_addr_r=0x90100000\0" \
  57        "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  58        "fdt_addr_r=0x82000000\0" \
  59        "ramdisk_addr_r=0x82100000\0"
  60
  61#endif
  62