1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2018 4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc 5 */ 6 7#ifndef DT_BINDINGS_MPC83XX_SDRAM_H 8#define DT_BINDINGS_MPC83XX_SDRAM_H 9 10/* DDR Control Driver register */ 11 12#define DSO_DISABLE 0 13#define DSO_ENABLE 1 14 15#define DSO_P_IMPEDANCE_HIGHEST_Z 0x0 16#define DSO_P_IMPEDANCE_MUCH_HIGHER_Z 0x8 17#define DSO_P_IMPEDANCE_HIGHER_Z 0xC 18#define DSO_P_IMPEDANCE_NOMINAL 0xE 19#define DSO_P_IMPEDANCE_LOWER_Z 0xF 20 21#define DSO_N_IMPEDANCE_HIGHEST_Z 0x0 22#define DSO_N_IMPEDANCE_MUCH_HIGHER_Z 0x8 23#define DSO_N_IMPEDANCE_HIGHER_Z 0xC 24#define DSO_N_IMPEDANCE_NOMINAL 0xE 25#define DSO_N_IMPEDANCE_LOWER_Z 0xF 26 27#define ODT_TERMINATION_75_OHM 0 28#define ODT_TERMINATION_150_OHM 1 29 30#define DDR_TYPE_DDR2_1_8_VOLT 0 31#define DDR_TYPE_DDR1_2_5_VOLT 1 32 33#define MVREF_SEL_EXTERNAL 0 34#define MVREF_SEL_INTERNAL_GVDD 1 35 36#define M_ODR_ENABLE 0 37#define M_ODR_DISABLE 1 38 39/* CS config register */ 40 41#define AUTO_PRECHARGE_ENABLE 0x00800000 42#define AUTO_PRECHARGE_DISABLE 0x00000000 43 44#define ODT_RD_NEVER 0x00000000 45#define ODT_RD_ONLY_CURRENT 0x00100000 46#define ODT_RD_ONLY_OTHER_CS 0x00200000 47#define ODT_RD_ONLY_OTHER_DIMM 0x00300000 48#define ODT_RD_ALL 0x00400000 49 50#define ODT_WR_NEVER 0x00000000 51#define ODT_WR_ONLY_CURRENT 0x00010000 52#define ODT_WR_ONLY_OTHER_CS 0x00020000 53#define ODT_WR_ONLY_OTHER_DIMM 0x00030000 54#define ODT_WR_ALL 0x00040000 55 56/* DDR SDRAM Clock Control register */ 57 58#define CLOCK_ADJUST_025 0x01000000 59#define CLOCK_ADJUST_05 0x02000000 60#define CLOCK_ADJUST_075 0x03000000 61#define CLOCK_ADJUST_1 0x04000000 62 63#define CASLAT_20 0x3 /* CAS latency = 2.0 */ 64#define CASLAT_25 0x4 /* CAS latency = 2.5 */ 65#define CASLAT_30 0x5 /* CAS latency = 3.0 */ 66#define CASLAT_35 0x6 /* CAS latency = 3.5 */ 67#define CASLAT_40 0x7 /* CAS latency = 4.0 */ 68#define CASLAT_45 0x8 /* CAS latency = 4.5 */ 69#define CASLAT_50 0x9 /* CAS latency = 5.0 */ 70#define CASLAT_55 0xa /* CAS latency = 5.5 */ 71#define CASLAT_60 0xb /* CAS latency = 6.0 */ 72#define CASLAT_65 0xc /* CAS latency = 6.5 */ 73#define CASLAT_70 0xd /* CAS latency = 7.0 */ 74#define CASLAT_75 0xe /* CAS latency = 7.5 */ 75#define CASLAT_80 0xf /* CAS latency = 8.0 */ 76 77/* DDR SDRAM Timing Configuration 2 register */ 78 79#define READ_LAT_PLUS_1 0x0 80#define READ_LAT 0x2 81#define READ_LAT_PLUS_1_4 0x3 82#define READ_LAT_PLUS_1_2 0x4 83#define READ_LAT_PLUS_3_4 0x5 84#define READ_LAT_PLUS_5_4 0x7 85#define READ_LAT_PLUS_3_2 0x8 86#define READ_LAT_PLUS_7_4 0x9 87#define READ_LAT_PLUS_2 0xA 88#define READ_LAT_PLUS_9_4 0xB 89#define READ_LAT_PLUS_5_2 0xC 90#define READ_LAT_PLUS_11_4 0xD 91#define READ_LAT_PLUS_3 0xE 92#define READ_LAT_PLUS_13_4 0xF 93#define READ_LAT_PLUS_7_2 0x10 94#define READ_LAT_PLUS_15_4 0x11 95#define READ_LAT_PLUS_4 0x12 96#define READ_LAT_PLUS_17_4 0x13 97#define READ_LAT_PLUS_9_2 0x14 98#define READ_LAT_PLUS_19_4 0x15 99 100#define CLOCK_DELAY_0 0x0 101#define CLOCK_DELAY_1_4 0x1 102#define CLOCK_DELAY_1_2 0x2 103#define CLOCK_DELAY_3_4 0x3 104#define CLOCK_DELAY_1 0x4 105#define CLOCK_DELAY_5_4 0x5 106#define CLOCK_DELAY_3_2 0x6 107 108/* DDR SDRAM Control Configuration */ 109 110#define SREN_DISABLE 0x0 111#define SREN_ENABLE 0x1 112 113#define ECC_DISABLE 0x0 114#define ECC_ENABLE 0x1 115 116#define RD_DISABLE 0x0 117#define RD_ENABLE 0x1 118 119#define TYPE_DDR1 0x2 120#define TYPE_DDR2 0x3 121 122#define DYN_PWR_DISABLE 0x0 123#define DYN_PWR_ENABLE 0x1 124 125#define DATA_BUS_WIDTH_16 0x1 126#define DATA_BUS_WIDTH_32 0x2 127 128#define NCAP_DISABLE 0x0 129#define NCAP_ENABLE 0x1 130 131#define TIMING_1T 0x0 132#define TIMING_2T 0x1 133 134#define INTERLEAVE_NONE 0x0 135#define INTERLEAVE_1_AND_2 0x1 136 137#define PRECHARGE_MA_10 0x0 138#define PRECHARGE_MA_8 0x1 139 140#define STRENGTH_FULL 0x0 141#define STRENGTH_HALF 0x1 142 143#define INITIALIZATION_DONT_BYPASS 0x0 144#define INITIALIZATION_BYPASS 0x1 145 146/* DDR SDRAM Control Configuration 2 register */ 147 148#define MODE_NORMAL 0x0 149#define MODE_REFRESH 0x1 150 151#define DLL_RESET_ENABLE 0x0 152#define DLL_RESET_DISABLE 0x1 153 154#define DQS_TRUE 0x0 155 156#define ODT_ASSERT_NEVER 0x0 157#define ODT_ASSERT_WRITES 0x1 158#define ODT_ASSERT_READS 0x2 159#define ODT_ASSERT_ALWAYS 0x3 160 161#endif 162