1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2008 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 */ 7 8#ifndef _KWBIMAGE_H_ 9#define _KWBIMAGE_H_ 10 11#include <compiler.h> 12#include <stdint.h> 13 14#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config)) 15#define MAX_TEMPBUF_LEN 32 16 17/* NAND ECC Mode */ 18#define IBR_HDR_ECC_DEFAULT 0x00 19#define IBR_HDR_ECC_FORCED_HAMMING 0x01 20#define IBR_HDR_ECC_FORCED_RS 0x02 21#define IBR_HDR_ECC_DISABLED 0x03 22 23/* Boot Type - block ID */ 24#define IBR_HDR_I2C_ID 0x4D 25#define IBR_HDR_SPI_ID 0x5A 26#define IBR_HDR_NAND_ID 0x8B 27#define IBR_HDR_SATA_ID 0x78 28#define IBR_HDR_PEX_ID 0x9C 29#define IBR_HDR_UART_ID 0x69 30#define IBR_DEF_ATTRIB 0x00 31 32/* Structure of the main header, version 0 (Kirkwood, Dove) */ 33struct main_hdr_v0 { 34 uint8_t blockid; /* 0x0 */ 35 uint8_t nandeccmode; /* 0x1 */ 36 uint16_t nandpagesize; /* 0x2-0x3 */ 37 uint32_t blocksize; /* 0x4-0x7 */ 38 uint32_t rsvd1; /* 0x8-0xB */ 39 uint32_t srcaddr; /* 0xC-0xF */ 40 uint32_t destaddr; /* 0x10-0x13 */ 41 uint32_t execaddr; /* 0x14-0x17 */ 42 uint8_t satapiomode; /* 0x18 */ 43 uint8_t rsvd3; /* 0x19 */ 44 uint16_t ddrinitdelay; /* 0x1A-0x1B */ 45 uint16_t rsvd2; /* 0x1C-0x1D */ 46 uint8_t ext; /* 0x1E */ 47 uint8_t checksum; /* 0x1F */ 48}; 49 50struct ext_hdr_v0_reg { 51 uint32_t raddr; 52 uint32_t rdata; 53}; 54 55#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg)) 56 57struct ext_hdr_v0 { 58 uint32_t offset; 59 uint8_t reserved[0x20 - sizeof(uint32_t)]; 60 struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT]; 61 uint8_t reserved2[7]; 62 uint8_t checksum; 63}; 64 65struct kwb_header { 66 struct main_hdr_v0 kwb_hdr; 67 struct ext_hdr_v0 kwb_exthdr; 68}; 69 70/* Structure of the main header, version 1 (Armada 370/38x/XP) */ 71struct main_hdr_v1 { 72 uint8_t blockid; /* 0x0 */ 73 uint8_t flags; /* 0x1 */ 74 uint16_t reserved2; /* 0x2-0x3 */ 75 uint32_t blocksize; /* 0x4-0x7 */ 76 uint8_t version; /* 0x8 */ 77 uint8_t headersz_msb; /* 0x9 */ 78 uint16_t headersz_lsb; /* 0xA-0xB */ 79 uint32_t srcaddr; /* 0xC-0xF */ 80 uint32_t destaddr; /* 0x10-0x13 */ 81 uint32_t execaddr; /* 0x14-0x17 */ 82 uint8_t options; /* 0x18 */ 83 uint8_t nandblocksize; /* 0x19 */ 84 uint8_t nandbadblklocation; /* 0x1A */ 85 uint8_t reserved4; /* 0x1B */ 86 uint16_t reserved5; /* 0x1C-0x1D */ 87 uint8_t ext; /* 0x1E */ 88 uint8_t checksum; /* 0x1F */ 89}; 90 91/* 92 * Main header options 93 */ 94#define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0 95#define MAIN_HDR_V1_OPT_BAUD_2400 0x1 96#define MAIN_HDR_V1_OPT_BAUD_4800 0x2 97#define MAIN_HDR_V1_OPT_BAUD_9600 0x3 98#define MAIN_HDR_V1_OPT_BAUD_19200 0x4 99#define MAIN_HDR_V1_OPT_BAUD_38400 0x5 100#define MAIN_HDR_V1_OPT_BAUD_57600 0x6 101#define MAIN_HDR_V1_OPT_BAUD_115200 0x7 102 103/* 104 * Header for the optional headers, version 1 (Armada 370, Armada XP) 105 */ 106struct opt_hdr_v1 { 107 uint8_t headertype; 108 uint8_t headersz_msb; 109 uint16_t headersz_lsb; 110 char data[0]; 111}; 112 113/* 114 * Public Key data in DER format 115 */ 116struct pubkey_der_v1 { 117 uint8_t key[524]; 118}; 119 120/* 121 * Signature (RSA 2048) 122 */ 123struct sig_v1 { 124 uint8_t sig[256]; 125}; 126 127/* 128 * Structure of secure header (Armada 38x) 129 */ 130struct secure_hdr_v1 { 131 uint8_t headertype; /* 0x0 */ 132 uint8_t headersz_msb; /* 0x1 */ 133 uint16_t headersz_lsb; /* 0x2 - 0x3 */ 134 uint32_t reserved1; /* 0x4 - 0x7 */ 135 struct pubkey_der_v1 kak; /* 0x8 - 0x213 */ 136 uint8_t jtag_delay; /* 0x214 */ 137 uint8_t reserved2; /* 0x215 */ 138 uint16_t reserved3; /* 0x216 - 0x217 */ 139 uint32_t boxid; /* 0x218 - 0x21B */ 140 uint32_t flashid; /* 0x21C - 0x21F */ 141 struct sig_v1 hdrsig; /* 0x220 - 0x31F */ 142 struct sig_v1 imgsig; /* 0x320 - 0x41F */ 143 struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */ 144 struct sig_v1 csksig; /* 0x24E0 - 0x25DF */ 145 uint8_t next; /* 0x25E0 */ 146 uint8_t reserved4; /* 0x25E1 */ 147 uint16_t reserved5; /* 0x25E2 - 0x25E3 */ 148}; 149 150/* 151 * Various values for the opt_hdr_v1->headertype field, describing the 152 * different types of optional headers. The "secure" header contains 153 * informations related to secure boot (encryption keys, etc.). The 154 * "binary" header contains ARM binary code to be executed prior to 155 * executing the main payload (usually the bootloader). This is 156 * typically used to execute DDR3 training code. The "register" header 157 * allows to describe a set of (address, value) tuples that are 158 * generally used to configure the DRAM controller. 159 */ 160#define OPT_HDR_V1_SECURE_TYPE 0x1 161#define OPT_HDR_V1_BINARY_TYPE 0x2 162#define OPT_HDR_V1_REGISTER_TYPE 0x3 163 164#define KWBHEADER_V1_SIZE(hdr) \ 165 (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb)) 166 167enum kwbimage_cmd { 168 CMD_INVALID, 169 CMD_BOOT_FROM, 170 CMD_NAND_ECC_MODE, 171 CMD_NAND_PAGE_SIZE, 172 CMD_SATA_PIO_MODE, 173 CMD_DDR_INIT_DELAY, 174 CMD_DATA 175}; 176 177enum kwbimage_cmd_types { 178 CFG_INVALID = -1, 179 CFG_COMMAND, 180 CFG_DATA0, 181 CFG_DATA1 182}; 183 184/* 185 * functions 186 */ 187void init_kwb_image_type (void); 188 189/* 190 * Byte 8 of the image header contains the version number. In the v0 191 * header, byte 8 was reserved, and always set to 0. In the v1 header, 192 * byte 8 has been changed to a proper field, set to 1. 193 */ 194static inline unsigned int image_version(void *header) 195{ 196 unsigned char *ptr = header; 197 return ptr[8]; 198} 199 200#endif /* _KWBIMAGE_H_ */ 201