LXR uboot/arch/arm/cpu/arm926ejs/armada100/cpu.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2010
   4 * Marvell Semiconductor <www.marvell.com>
   5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   6 * Contributor: Mahavir Jain <mjain@marvell.com>
   7 */
   8
   9#include <common.h>
  10#include <cpu_func.h>
  11#include <init.h>
  12#include <asm/arch/cpu.h>
  13#include <asm/arch/armada100.h>
  14
  15#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
  16#define SET_MRVL_ID     (1<<8)
  17#define L2C_RAM_SEL     (1<<4)
  18
  19int arch_cpu_init(void)
  20{
  21        u32 val;
  22        struct armd1cpu_registers *cpuregs =
  23                (struct armd1cpu_registers *) ARMD1_CPU_BASE;
  24
  25        struct armd1apb1_registers *apb1clkres =
  26                (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
  27
  28        struct armd1mpmu_registers *mpmu =
  29                (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
  30
  31        /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
  32        val = readl(&cpuregs->cpu_conf);
  33        val = val | SET_MRVL_ID;
  34        writel(val, &cpuregs->cpu_conf);
  35
  36        /* Enable Clocks for all hardware units */
  37        writel(0xFFFFFFFF, &mpmu->acgr);
  38
  39        /* Turn on AIB and AIB-APB Functional clock */
  40        writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
  41
  42        /* ensure L2 cache is not mapped as SRAM */
  43        val = readl(&cpuregs->cpu_conf);
  44        val = val & ~(L2C_RAM_SEL);
  45        writel(val, &cpuregs->cpu_conf);
  46
  47        /* Enable GPIO clock */
  48        writel(APBC_APBCLK, &apb1clkres->gpio);
  49
  50#ifdef CONFIG_I2C_MV
  51        /* Enable general I2C clock */
  52        writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
  53        writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
  54
  55        /* Enable power I2C clock */
  56        writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
  57        writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
  58#endif
  59
  60        /*
  61         * Enable Functional and APB clock at 14.7456MHz
  62         * for configured UART console
  63         */
  64#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
  65        writel(UARTCLK14745KHZ, &apb1clkres->uart3);
  66#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
  67        writel(UARTCLK14745KHZ, &apb1clkres->uart2);
  68#else
  69        writel(UARTCLK14745KHZ, &apb1clkres->uart1);
  70#endif
  71        icache_enable();
  72
  73        return 0;
  74}
  75
  76#if defined(CONFIG_DISPLAY_CPUINFO)
  77int print_cpuinfo(void)
  78{
  79        u32 id;
  80        struct armd1cpu_registers *cpuregs =
  81                (struct armd1cpu_registers *) ARMD1_CPU_BASE;
  82
  83        id = readl(&cpuregs->chip_id);
  84        printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
  85        return 0;
  86}
  87#endif
  88
  89#ifdef CONFIG_I2C_MV
  90void i2c_clk_enable(void)
  91{
  92}
  93#endif
  94