uboot/arch/arm/include/asm/arch-mx6/clock.h
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   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2009
   4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   5 */
   6
   7#ifndef __ASM_ARCH_CLOCK_H
   8#define __ASM_ARCH_CLOCK_H
   9
  10#include <linux/types.h>
  11
  12#ifdef CONFIG_SYS_MX6_HCLK
  13#define MXC_HCLK        CONFIG_SYS_MX6_HCLK
  14#else
  15#define MXC_HCLK        24000000
  16#endif
  17
  18#ifdef CONFIG_SYS_MX6_CLK32
  19#define MXC_CLK32       CONFIG_SYS_MX6_CLK32
  20#else
  21#define MXC_CLK32       32768
  22#endif
  23
  24struct cmd_tbl;
  25
  26enum mxc_clock {
  27        MXC_ARM_CLK = 0,
  28        MXC_PER_CLK,
  29        MXC_AHB_CLK,
  30        MXC_IPG_CLK,
  31        MXC_IPG_PERCLK,
  32        MXC_UART_CLK,
  33        MXC_CSPI_CLK,
  34        MXC_AXI_CLK,
  35        MXC_EMI_SLOW_CLK,
  36        MXC_DDR_CLK,
  37        MXC_ESDHC_CLK,
  38        MXC_ESDHC2_CLK,
  39        MXC_ESDHC3_CLK,
  40        MXC_ESDHC4_CLK,
  41        MXC_SATA_CLK,
  42        MXC_NFC_CLK,
  43        MXC_I2C_CLK,
  44};
  45
  46enum ldb_di_clock {
  47        MXC_PLL5_CLK = 0,
  48        MXC_PLL2_PFD0_CLK,
  49        MXC_PLL2_PFD2_CLK,
  50        MXC_MMDC_CH1_CLK,
  51        MXC_PLL3_SW_CLK,
  52};
  53
  54enum enet_freq {
  55        ENET_25MHZ,
  56        ENET_50MHZ,
  57        ENET_100MHZ,
  58        ENET_125MHZ,
  59};
  60
  61u32 imx_get_uartclk(void);
  62u32 imx_get_fecclk(void);
  63unsigned int mxc_get_clock(enum mxc_clock clk);
  64void setup_gpmi_io_clk(u32 cfg);
  65void hab_caam_clock_enable(unsigned char enable);
  66void enable_ocotp_clk(unsigned char enable);
  67void enable_usboh3_clk(unsigned char enable);
  68void enable_uart_clk(unsigned char enable);
  69int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
  70int enable_sata_clock(void);
  71void disable_sata_clock(void);
  72int enable_pcie_clock(void);
  73int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
  74int enable_spi_clk(unsigned char enable, unsigned spi_num);
  75void enable_ipu_clock(void);
  76void disable_ipu_clock(void);
  77int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
  78void enable_enet_clk(unsigned char enable);
  79int enable_lcdif_clock(u32 base_addr, bool enable);
  80void enable_qspi_clk(int qspi_num);
  81void enable_thermal_clk(void);
  82void mxs_set_lcdclk(u32 base_addr, u32 freq);
  83void select_ldb_di_clock_source(enum ldb_di_clock clk);
  84void enable_eim_clk(unsigned char enable);
  85int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  86                      char *const argv[]);
  87#endif /* __ASM_ARCH_CLOCK_H */
  88