LXR uboot/arch/arm/include/asm/arch-rockchip/clock.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * (C) Copyright 2015 Google, Inc
   4 */
   5
   6#ifndef _ASM_ARCH_CLOCK_H
   7#define _ASM_ARCH_CLOCK_H
   8
   9struct udevice;
  10
  11/* define pll mode */
  12#define RKCLK_PLL_MODE_SLOW             0
  13#define RKCLK_PLL_MODE_NORMAL           1
  14#define RKCLK_PLL_MODE_DEEP             2
  15
  16enum {
  17        ROCKCHIP_SYSCON_NOC,
  18        ROCKCHIP_SYSCON_GRF,
  19        ROCKCHIP_SYSCON_SGRF,
  20        ROCKCHIP_SYSCON_PMU,
  21        ROCKCHIP_SYSCON_PMUGRF,
  22        ROCKCHIP_SYSCON_PMUSGRF,
  23        ROCKCHIP_SYSCON_CIC,
  24        ROCKCHIP_SYSCON_MSCH,
  25};
  26
  27/* Standard Rockchip clock numbers */
  28enum rk_clk_id {
  29        CLK_OSC,
  30        CLK_ARM,
  31        CLK_DDR,
  32        CLK_CODEC,
  33        CLK_GENERAL,
  34        CLK_NEW,
  35
  36        CLK_COUNT,
  37};
  38
  39#define PLL(_type, _id, _con, _mode, _mshift,                   \
  40                 _lshift, _pflags, _rtable)                     \
  41        {                                                       \
  42                .id             = _id,                          \
  43                .type           = _type,                        \
  44                .con_offset     = _con,                         \
  45                .mode_offset    = _mode,                        \
  46                .mode_shift     = _mshift,                      \
  47                .lock_shift     = _lshift,                      \
  48                .pll_flags      = _pflags,                      \
  49                .rate_table     = _rtable,                      \
  50        }
  51
  52#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,      \
  53                        _postdiv2, _dsmpd, _frac)               \
  54{                                                               \
  55        .rate   = _rate##U,                                     \
  56        .fbdiv = _fbdiv,                                        \
  57        .postdiv1 = _postdiv1,                                  \
  58        .refdiv = _refdiv,                                      \
  59        .postdiv2 = _postdiv2,                                  \
  60        .dsmpd = _dsmpd,                                        \
  61        .frac = _frac,                                          \
  62}
  63
  64struct rockchip_pll_rate_table {
  65        unsigned long rate;
  66        unsigned int nr;
  67        unsigned int nf;
  68        unsigned int no;
  69        unsigned int nb;
  70        /* for RK3036/RK3399 */
  71        unsigned int fbdiv;
  72        unsigned int postdiv1;
  73        unsigned int refdiv;
  74        unsigned int postdiv2;
  75        unsigned int dsmpd;
  76        unsigned int frac;
  77};
  78
  79enum rockchip_pll_type {
  80        pll_rk3036,
  81        pll_rk3066,
  82        pll_rk3328,
  83        pll_rk3366,
  84        pll_rk3399,
  85};
  86
  87struct rockchip_pll_clock {
  88        unsigned int                    id;
  89        unsigned int                    con_offset;
  90        unsigned int                    mode_offset;
  91        unsigned int                    mode_shift;
  92        unsigned int                    lock_shift;
  93        enum rockchip_pll_type          type;
  94        unsigned int                    pll_flags;
  95        struct rockchip_pll_rate_table *rate_table;
  96        unsigned int                    mode_mask;
  97};
  98
  99struct rockchip_cpu_rate_table {
 100        unsigned long rate;
 101        unsigned int aclk_div;
 102        unsigned int pclk_div;
 103};
 104
 105int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
 106                          void __iomem *base, ulong clk_id,
 107                          ulong drate);
 108ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
 109                            void __iomem *base, ulong clk_id);
 110const struct rockchip_cpu_rate_table *
 111rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
 112                          ulong rate);
 113
 114static inline int rk_pll_id(enum rk_clk_id clk_id)
 115{
 116        return clk_id - 1;
 117}
 118
 119struct sysreset_reg {
 120        unsigned int glb_srst_fst_value;
 121        unsigned int glb_srst_snd_value;
 122};
 123
 124/**
 125 * clk_get_divisor() - Calculate the required clock divisior
 126 *
 127 * Given an input rate and a required output_rate, calculate the Rockchip
 128 * divisor needed to achieve this.
 129 *
 130 * @input_rate:         Input clock rate in Hz
 131 * @output_rate:        Output clock rate in Hz
 132 * @return divisor register value to use
 133 */
 134static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
 135{
 136        uint clk_div;
 137
 138        clk_div = input_rate / output_rate;
 139        clk_div = (clk_div + 1) & 0xfffe;
 140
 141        return clk_div;
 142}
 143
 144/**
 145 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
 146 *
 147 * @return pointer to registers, or -ve error on error
 148 */
 149void *rockchip_get_cru(void);
 150
 151/**
 152 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
 153 *
 154 * @return pointer to registers, or -ve error on error
 155 */
 156void *rockchip_get_pmucru(void);
 157
 158struct rockchip_cru;
 159struct rk3288_grf;
 160
 161void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
 162
 163int rockchip_get_clk(struct udevice **devp);
 164
 165/*
 166 * rockchip_reset_bind() - Bind soft reset device as child of clock device
 167 *
 168 * @pdev: clock udevice
 169 * @reg_offset: the first offset in cru for softreset registers
 170 * @reg_number: the reg numbers of softreset registers
 171 * @return 0 success, or error value
 172 */
 173int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
 174
 175#endif
 176