LXR uboot/arch/arm/include/asm/ti-common/omap

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * omap_wdt.h
   4 *
   5 * OMAP Watchdog header file
   6 *
   7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8 */
   9
  10#ifndef __OMAP_WDT_H__
  11#define __OMAP_WDT_H__
  12
  13#ifndef __ASSEMBLY__
  14#include <linux/bitops.h>
  15#endif
  16
  17/*
  18 * Watchdog:
  19 * Using the prescaler, the OMAP watchdog could go for many
  20 * months before firing.  These limits work without scaling,
  21 * with the 60 second default assumed by most tools and docs.
  22 */
  23#define TIMER_MARGIN_MAX        (24 * 60 * 60)  /* 1 day */
  24#define TIMER_MARGIN_DEFAULT    60      /* 60 secs */
  25#define TIMER_MARGIN_MIN        1
  26
  27#define PTV                     0       /* prescale */
  28#define GET_WLDR_VAL(secs)      (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
  29#define WDT_WWPS_PEND_WCLR      BIT(0)
  30#define WDT_WWPS_PEND_WLDR      BIT(2)
  31#define WDT_WWPS_PEND_WTGR      BIT(3)
  32#define WDT_WWPS_PEND_WSPR      BIT(4)
  33
  34#define WDT_WCLR_PRE            BIT(5)
  35#define WDT_WCLR_PTV_OFF        2
  36
  37/* Watchdog timer registers */
  38struct wd_timer {
  39        unsigned int resv1[4];
  40        unsigned int wdtwdsc;   /* offset 0x010 */
  41        unsigned int wdtwdst;   /* offset 0x014 */
  42        unsigned int wdtwisr;   /* offset 0x018 */
  43        unsigned int wdtwier;   /* offset 0x01C */
  44        unsigned int wdtwwer;   /* offset 0x020 */
  45        unsigned int wdtwclr;   /* offset 0x024 */
  46        unsigned int wdtwcrr;   /* offset 0x028 */
  47        unsigned int wdtwldr;   /* offset 0x02C */
  48        unsigned int wdtwtgr;   /* offset 0x030 */
  49        unsigned int wdtwwps;   /* offset 0x034 */
  50        unsigned int resv2[3];
  51        unsigned int wdtwdly;   /* offset 0x044 */
  52        unsigned int wdtwspr;   /* offset 0x048 */
  53        unsigned int resv3[1];
  54        unsigned int wdtwqeoi;  /* offset 0x050 */
  55        unsigned int wdtwqstar; /* offset 0x054 */
  56        unsigned int wdtwqsta;  /* offset 0x058 */
  57        unsigned int wdtwqens;  /* offset 0x05C */
  58        unsigned int wdtwqenc;  /* offset 0x060 */
  59        unsigned int resv4[39];
  60        unsigned int wdt_unfr;  /* offset 0x100 */
  61};
  62
  63struct omap3_wdt_priv {
  64        struct wd_timer *regs;
  65        unsigned int wdt_trgr_pattern;
  66};
  67
  68#endif /* __OMAP_WDT_H__ */
  69