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10#include <common.h>
11#include <dm.h>
12#include <debug_uart.h>
13#include <errno.h>
14#include <init.h>
15#include <net.h>
16#include <ns16550.h>
17#include <omap3_spi.h>
18#include <spl.h>
19#include <asm/arch/cpu.h>
20#include <asm/arch/hardware.h>
21#include <asm/arch/omap.h>
22#include <asm/arch/ddr_defs.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/gpio.h>
25#include <asm/arch/i2c.h>
26#include <asm/arch/mem.h>
27#include <asm/arch/mmc_host_def.h>
28#include <asm/arch/sys_proto.h>
29#include <asm/global_data.h>
30#include <asm/io.h>
31#include <asm/emif.h>
32#include <asm/gpio.h>
33#include <asm/omap_common.h>
34#include <i2c.h>
35#include <miiphy.h>
36#include <cpsw.h>
37#include <linux/delay.h>
38#include <linux/errno.h>
39#include <linux/compiler.h>
40#include <linux/usb/ch9.h>
41#include <linux/usb/gadget.h>
42#include <linux/usb/musb.h>
43#include <asm/omap_musb.h>
44#include <asm/davinci_rtc.h>
45
46#define AM43XX_EMIF_BASE 0x4C000000
47#define AM43XX_SDRAM_CONFIG_OFFSET 0x8
48#define AM43XX_SDRAM_TYPE_MASK 0xE0000000
49#define AM43XX_SDRAM_TYPE_SHIFT 29
50#define AM43XX_SDRAM_TYPE_DDR3 3
51#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
52#define AM43XX_RDWRLVLFULL_START 0x80000000
53
54
55#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
56#define AM33XX_SPI0_BASE 0x48030000
57#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
58#endif
59
60DECLARE_GLOBAL_DATA_PTR;
61
62int dram_init(void)
63{
64#ifndef CONFIG_SKIP_LOWLEVEL_INIT
65 sdram_init();
66#endif
67
68
69 gd->ram_size = get_ram_size(
70 (void *)CONFIG_SYS_SDRAM_BASE,
71 CONFIG_MAX_RAM_BANK_SIZE);
72 return 0;
73}
74
75int dram_init_banksize(void)
76{
77 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
78 gd->bd->bi_dram[0].size = gd->ram_size;
79
80 return 0;
81}
82
83#if !CONFIG_IS_ENABLED(OF_CONTROL)
84static const struct ns16550_plat am33xx_serial[] = {
85 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
86 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
87# ifdef CONFIG_SYS_NS16550_COM2
88 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
89 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
90# ifdef CONFIG_SYS_NS16550_COM3
91 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
92 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
93 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
94 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
95 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
96 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
97 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
98 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
99# endif
100# endif
101};
102
103U_BOOT_DRVINFOS(am33xx_uarts) = {
104 { "ns16550_serial", &am33xx_serial[0] },
105# ifdef CONFIG_SYS_NS16550_COM2
106 { "ns16550_serial", &am33xx_serial[1] },
107# ifdef CONFIG_SYS_NS16550_COM3
108 { "ns16550_serial", &am33xx_serial[2] },
109 { "ns16550_serial", &am33xx_serial[3] },
110 { "ns16550_serial", &am33xx_serial[4] },
111 { "ns16550_serial", &am33xx_serial[5] },
112# endif
113# endif
114};
115
116#if CONFIG_IS_ENABLED(DM_I2C)
117static const struct omap_i2c_plat am33xx_i2c[] = {
118 { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
119 { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
120 { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
121};
122
123U_BOOT_DRVINFOS(am33xx_i2c) = {
124 { "i2c_omap", &am33xx_i2c[0] },
125 { "i2c_omap", &am33xx_i2c[1] },
126 { "i2c_omap", &am33xx_i2c[2] },
127};
128#endif
129
130#if CONFIG_IS_ENABLED(DM_GPIO)
131static const struct omap_gpio_plat am33xx_gpio[] = {
132 { 0, AM33XX_GPIO0_BASE },
133 { 1, AM33XX_GPIO1_BASE },
134 { 2, AM33XX_GPIO2_BASE },
135 { 3, AM33XX_GPIO3_BASE },
136#ifdef CONFIG_AM43XX
137 { 4, AM33XX_GPIO4_BASE },
138 { 5, AM33XX_GPIO5_BASE },
139#endif
140};
141
142U_BOOT_DRVINFOS(am33xx_gpios) = {
143 { "gpio_omap", &am33xx_gpio[0] },
144 { "gpio_omap", &am33xx_gpio[1] },
145 { "gpio_omap", &am33xx_gpio[2] },
146 { "gpio_omap", &am33xx_gpio[3] },
147#ifdef CONFIG_AM43XX
148 { "gpio_omap", &am33xx_gpio[4] },
149 { "gpio_omap", &am33xx_gpio[5] },
150#endif
151};
152#endif
153#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
154static const struct omap3_spi_plat omap3_spi_pdata = {
155 .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
156 .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
157};
158
159U_BOOT_DRVINFO(am33xx_spi) = {
160 .name = "omap3_spi",
161 .plat = &omap3_spi_pdata,
162};
163#endif
164#endif
165
166#if !CONFIG_IS_ENABLED(DM_GPIO)
167static const struct gpio_bank gpio_bank_am33xx[] = {
168 { (void *)AM33XX_GPIO0_BASE },
169 { (void *)AM33XX_GPIO1_BASE },
170 { (void *)AM33XX_GPIO2_BASE },
171 { (void *)AM33XX_GPIO3_BASE },
172#ifdef CONFIG_AM43XX
173 { (void *)AM33XX_GPIO4_BASE },
174 { (void *)AM33XX_GPIO5_BASE },
175#endif
176};
177
178const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
179#endif
180
181#if defined(CONFIG_MMC_OMAP_HS)
182int cpu_mmc_init(struct bd_info *bis)
183{
184 int ret;
185
186 ret = omap_mmc_init(0, 0, 0, -1, -1);
187 if (ret)
188 return ret;
189
190 return omap_mmc_init(1, 0, 0, -1, -1);
191}
192#endif
193
194
195
196
197
198
199#define RTC_MAGIC_VAL 0x8cd0
200
201
202#define RTC_BOARD_TYPE_SHIFT 16
203
204
205#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
206 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
207 (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
208 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
209
210static struct musb_hdrc_config musb_config = {
211 .multipoint = 1,
212 .dyn_fifo = 1,
213 .num_eps = 16,
214 .ram_bits = 12,
215};
216
217#if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
218static struct ti_musb_plat usb0 = {
219 .base = (void *)USB0_OTG_BASE,
220 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
221 .plat = {
222 .config = &musb_config,
223 .power = 50,
224 .platform_ops = &musb_dsps_ops,
225 },
226};
227
228static struct ti_musb_plat usb1 = {
229 .base = (void *)USB1_OTG_BASE,
230 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
231 .plat = {
232 .config = &musb_config,
233 .power = 50,
234 .platform_ops = &musb_dsps_ops,
235 },
236};
237
238U_BOOT_DRVINFOS(am33xx_usbs) = {
239#if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
240 { "ti-musb-peripheral", &usb0 },
241#elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
242 { "ti-musb-host", &usb0 },
243#endif
244#if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
245 { "ti-musb-peripheral", &usb1 },
246#elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
247 { "ti-musb-host", &usb1 },
248#endif
249};
250
251int arch_misc_init(void)
252{
253 return 0;
254}
255#else
256static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
257
258
259#define CM_PHY_PWRDN (1 << 0)
260#define CM_PHY_OTG_PWRDN (1 << 1)
261#define OTGVDET_EN (1 << 19)
262#define OTGSESSENDEN (1 << 20)
263
264static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
265{
266 if (on) {
267 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
268 OTGVDET_EN | OTGSESSENDEN);
269 } else {
270 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
271 }
272}
273
274#ifdef CONFIG_AM335X_USB0
275static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
276{
277 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
278}
279
280struct omap_musb_board_data otg0_board_data = {
281 .set_phy_power = am33xx_otg0_set_phy_power,
282};
283
284static struct musb_hdrc_platform_data otg0_plat = {
285 .mode = CONFIG_AM335X_USB0_MODE,
286 .config = &musb_config,
287 .power = 50,
288 .platform_ops = &musb_dsps_ops,
289 .board_data = &otg0_board_data,
290};
291#endif
292
293#ifdef CONFIG_AM335X_USB1
294static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
295{
296 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
297}
298
299struct omap_musb_board_data otg1_board_data = {
300 .set_phy_power = am33xx_otg1_set_phy_power,
301};
302
303static struct musb_hdrc_platform_data otg1_plat = {
304 .mode = CONFIG_AM335X_USB1_MODE,
305 .config = &musb_config,
306 .power = 50,
307 .platform_ops = &musb_dsps_ops,
308 .board_data = &otg1_board_data,
309};
310#endif
311
312int arch_misc_init(void)
313{
314#ifdef CONFIG_AM335X_USB0
315 musb_register(&otg0_plat, &otg0_board_data,
316 (void *)USB0_OTG_BASE);
317#endif
318#ifdef CONFIG_AM335X_USB1
319 musb_register(&otg1_plat, &otg1_board_data,
320 (void *)USB1_OTG_BASE);
321#endif
322 return 0;
323}
324#endif
325
326#else
327
328int arch_misc_init(void)
329{
330 struct udevice *dev;
331 int ret;
332
333 ret = uclass_first_device(UCLASS_MISC, &dev);
334 if (ret || !dev)
335 return ret;
336
337#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
338 ret = usb_ether_init();
339 if (ret) {
340 pr_err("USB ether init failed\n");
341 return ret;
342 }
343#endif
344
345 return 0;
346}
347
348#endif
349
350#ifndef CONFIG_SKIP_LOWLEVEL_INIT
351
352#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
353 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
354static void rtc32k_unlock(struct davinci_rtc *rtc)
355{
356
357
358
359
360
361 writel(RTC_KICK0R_WE, &rtc->kick0r);
362 writel(RTC_KICK1R_WE, &rtc->kick1r);
363}
364#endif
365
366#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
367
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369
370
371
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373
374
375
376
377
378
379void update_rtc_magic(void)
380{
381 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
382 u32 magic = RTC_MAGIC_VAL;
383
384 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
385
386 rtc32k_unlock(rtc);
387
388
389 writel(magic, &rtc->scratch1);
390}
391#endif
392
393
394
395
396
397
398int board_early_init_f(void)
399{
400 set_mux_conf_regs();
401 prcm_init();
402#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
403 update_rtc_magic();
404#endif
405 return 0;
406}
407
408
409
410
411
412__weak void am33xx_spl_board_init(void)
413{
414}
415
416#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
417static void rtc32k_enable(void)
418{
419 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
420
421 rtc32k_unlock(rtc);
422
423
424 writel((1 << 3) | (1 << 6), &rtc->osc);
425}
426#endif
427
428static void uart_soft_reset(void)
429{
430 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
431 u32 regval;
432
433 regval = readl(&uart_base->uartsyscfg);
434 regval |= UART_RESET;
435 writel(regval, &uart_base->uartsyscfg);
436 while ((readl(&uart_base->uartsyssts) &
437 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
438 ;
439
440
441 regval = readl(&uart_base->uartsyscfg);
442 regval |= UART_SMART_IDLE_EN;
443 writel(regval, &uart_base->uartsyscfg);
444}
445
446static void watchdog_disable(void)
447{
448 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
449
450 writel(0xAAAA, &wdtimer->wdtwspr);
451 while (readl(&wdtimer->wdtwwps) != 0x0)
452 ;
453 writel(0x5555, &wdtimer->wdtwspr);
454 while (readl(&wdtimer->wdtwwps) != 0x0)
455 ;
456}
457
458#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
459
460
461
462static void rtc_only(void)
463{
464 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
465 struct prm_device_inst *prm_device =
466 (struct prm_device_inst *)PRM_DEVICE_INST;
467
468 u32 scratch1, sdrc;
469 void (*resume_func)(void);
470
471 scratch1 = readl(&rtc->scratch1);
472
473
474
475
476
477
478
479
480 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
481 return;
482
483 rtc32k_unlock(rtc);
484
485
486 writel(0, &rtc->scratch1);
487
488
489
490
491
492
493 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
494
495
496
497
498
499
500
501 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
502
503 rtc_only_prcm_init();
504 sdram_init();
505
506
507
508 sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
509
510 sdrc &= AM43XX_SDRAM_TYPE_MASK;
511 sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
512
513 if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
514 writel(AM43XX_RDWRLVLFULL_START,
515 AM43XX_EMIF_BASE +
516 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
517 mdelay(1);
518
519am43xx_wait:
520 sdrc = readl(AM43XX_EMIF_BASE +
521 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
522 if (sdrc == AM43XX_RDWRLVLFULL_START)
523 goto am43xx_wait;
524 }
525
526 resume_func = (void *)readl(&rtc->scratch0);
527 if (resume_func)
528 resume_func();
529}
530#endif
531
532void s_init(void)
533{
534#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
535 rtc_only();
536#endif
537}
538
539void early_system_init(void)
540{
541
542
543
544
545
546#ifdef CONFIG_NOR_BOOT
547 enable_norboot_pin_mux();
548#endif
549 watchdog_disable();
550 set_uart_mux_conf();
551 setup_early_clocks();
552 uart_soft_reset();
553#ifdef CONFIG_SPL_BUILD
554
555
556
557
558
559 save_omap_boot_params();
560#endif
561#ifdef CONFIG_DEBUG_UART_OMAP
562 debug_uart_init();
563#endif
564
565#ifdef CONFIG_SPL_BUILD
566 spl_early_init();
567#endif
568
569#ifdef CONFIG_TI_I2C_BOARD_DETECT
570 do_board_detect();
571#endif
572
573#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
574
575 rtc32k_enable();
576#endif
577}
578
579#ifdef CONFIG_SPL_BUILD
580void board_init_f(ulong dummy)
581{
582 hw_data_init();
583 early_system_init();
584 board_early_init_f();
585 sdram_init();
586
587 gd->ram_size = get_ram_size(
588 (void *)CONFIG_SYS_SDRAM_BASE,
589 CONFIG_MAX_RAM_BANK_SIZE);
590}
591#endif
592
593#endif
594
595int arch_cpu_init_dm(void)
596{
597 hw_data_init();
598#ifndef CONFIG_SKIP_LOWLEVEL_INIT
599 early_system_init();
600#endif
601 return 0;
602}
603